arm: socfpga: Add Cadence QSPI support
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Cover letter [U-Boot] [PATCH 0/2 v3] arm: socfpga: Add Cadence QSPI support
Quoted 15 lines · Stefan Roese
Hi!
So this is my 3rd posting regarding the Candence SPI driver on SoCFPGA.
The current status is, that SPI NOR flash works now without problems. And dcache is still enabled. The previous disabling was not needed. And only caused problems while booting into Linux. No cache flush or invalidate is needed. As no DMA engine is involved in this transfer.
The "solution" I used to get SPI NOR flash support working now is implemented in patch 0004 (still marked as RFC). Here a software reset is issued on the Micron N25Q256A SPI NOR flash. This seems to solve all problems and reading / writing to the SPI NOR flash seems to work now just fine. Even rebooting via pushbutton-reset or reset command works.
Quoted 4 lines
I think this version is now in much better state. Thats why I removed the WIP from the subject lines.
Again, this is tested on the EBV SoCrates eval board.
I picked this up into u-boot-socfpga:topic/drivers/qspi-wip-20141003 so it doesn't get lost. Also, they are updated to use the latest socfpga stuff, esp. since the socfpga_cyclone5_common.h was renamed to socfpga_common.h .
Best regards,
Marek Vasut