ARM: DRA7: DDR3: Enable hw leveling
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b4 am 20150603141010.GL1728@bill-the-catVersions newest first
- v1 Latest7 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/7 | ARM: DRA7: DDR3: Add support for HW leveling | +0 | 0 replies | |
| 1/7 | ARM: DRA7: DDR3: Add support for HW leveling | +0 | 0 replies | |
| 2/7 | ARM: BeagleBoard-X15: Enable HW leveling | +0 | 0 replies | |
| 2/7 | ARM: BeagleBoard-X15: Enable HW leveling | +0 | 0 replies | |
| 3/7 | ARM: DRA7-evm: Enable HW leveling | +0 | 0 replies | |
| 3/7 | ARM: DRA7-evm: Enable HW leveling | +0 | 0 replies | |
| 4/7 | ARM: DRA72-evm: Enable HW leveling | +0 | 0 replies | |
| 4/7 | ARM: DRA72-evm: Enable HW leveling | +0 | 0 replies | |
| 5/7 | ARM: DRA7: Add is_dra72x cpu check definition | +0 | 0 replies | |
| 5/7 | ARM: DRA7: Add is_dra72x cpu check definition | +0 | 0 replies | |
| 6/7 | ARM: DRA7: Update DDR IO configuration | +0 | 0 replies | |
| 6/7 | ARM: DRA7: Update DDR IO configuration | +0 | 0 replies | |
| 7/7 | ARM: DRA7: Update DDR IO registers | +0 | 0 replies | |
| 7/7 | ARM: DRA7: Update DDR IO registers | +0 | 0 replies |
Reviews trailers per patch
All 14 patches have a Reviewed-by or Acked-by.
| Patch | Tom Rini |
|---|---|
| 1/7 | R-b |
| 1/7 | R-b |
| 2/7 | R-b |
| 2/7 | R-b |
| 3/7 | R-b |
| 3/7 | R-b |
| 4/7 | R-b |
| 4/7 | R-b |
| 5/7 | R-b |
| 5/7 | R-b |
| 6/7 | R-b |
| 6/7 | R-b |
| 7/7 | R-b |
| 7/7 | R-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [U-Boot] [PATCH 0/7] ARM: DRA7: DDR3: Enable hw leveling
Quoted 4 lines · Lokesh Vutla
This series updates the DDR3 init sequence and adds support for hw leveling for all DRA7 platforms.
Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards.
For sanity sake, tested on omap5_uevm (but indeed, the code didn't change just a few related calling paths for that family).
Signature · 8 lines
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