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socfpga: SPL and DDR init

Pavel Machek u-boot 1 version New

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  1. v1 Latest0 of 172 patches 0 repliesNew

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Cover letter [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init

Hi!

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+ rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
1);

(quoted diff) +3 -0
+       /*
+        * Need to wait tMOD (12CK or 15ns) time before issuing other
+        * commands, but we will have plenty of NIOS cycles before

actual

(quoted diff) +2 -0
+        * handoff so its okay.
+        */
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I don't understand this comment.

There's plenty of code between issuing the above instruction and triggering the mem handoff, so we don't need to add explicit delay into this function. Also, 15nS is like 15 instructions on the SoCFPGA, so there is zero chance we will trigger the handoff too early.

What does this have to do with NIOS? CPU cores in FPGA are not mandatory, AFAICT.

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It looks much better now, thanks,

It's far from good though and there will be another series after this one I'm afraid. It might be even heftier, but I want to open the door to proper SoCFPGA support this MW even if it means blowing them to shreds ...

MW?

Pavel

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