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spi: cadence_qspi: optimize & fix indirect rd-writes

Marek Vasut u-boot 5 versions – New

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  1. v4 Latest posting 2/20 of 5 patches 0 repliesNew
  2. v4 posting 1/20 of 5 patches 0 repliesSuperseded
  3. v1 posting 3/30 of 7 patches 0 repliesSuperseded
Earlier versions · 2
VersionPostedPatchesRepliesStatus
v1 posting 2/30 of 7 patches0 repliesSuperseded
v1 posting 1/30 of 7 patches0 repliesSuperseded

Patches in v4 posting 2/2 No applies recorded yet

None of the 5 patches the cover letter announces are in this archive.

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Cover letter [U-Boot] [RESEND PATCH v4 0/5] spi: cadence_qspi: optimize & fix indirect rd-writes
Quoted 16 lines · vikas

Hi,

Quoted 13 lines · Marek Vasut
Quoted 11 lines · Vikas Manocha

This patchset:
- fixes trigger base & transfer start address register programming. This fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger address setting".
- adds support to get fifo width from device tree

Changes in v4:
- fifo-width & trigger address alligned to linux device tree binding.
- renaming of one parameter splitted to separate patch.
- trigger address of socfpga reverted back to 0x0.
- code formatting done to avoid checkpatch CHECKS.

Quoted 7 lines
Quoted 4 lines

OK, this is obviously not 1:1 resend. The previous patchset had at least a different cover letter. So is this a V5 or what is this really ? Please do not tag "RESEND" stuff which actually contain modifications, this sort of behavior is absolutelly not helpful.

The intention of quick "RESEND v4" was for reviewers to ignore v4 to save their time. Let me know if i need to mark it v5.

Yes, it was supposed to be marked as V5 if it contained changes.

Best regards,
Marek Vasut

Read the cover letter in its thread