Enable MSR_TM lazily

Currently the kernel checks to see if the hardware is transactional memory capable and always enables the MSR_TM bit. The problem with this is that the TM related SPRs become available to userspace, requiring them to be switched between processes. It turns out these SPRs are expensive to read and write and if a thread doesn't use TM (or worse yet isn't even TM aware) then context switching incurs this penalty for nothing.

The solution here is to leave the MSR_TM bit disabled and enable it more 'on demand'. Leaving MSR_TM disabled cause a thread to take a facility unavailable fault if and when it does decide to use TM. As with recent updates to the FPU, VMX and VSX units the MSR_TM bit will be enabled upon taking the fault and left on for some time afterwards as the assumption is that if a thread used TM ones it may well use it again. The kernel will turn the MSR_TM bit off after some number of context switches of that thread.

Performance numbers haven't been completely gathered as yet but early runs of tools/testing/selftests/powerpc/benchmarks/context_switch (which doesn't use TM) yields a jump from ~160000 switches per second to ~180000 switches per second with patch 3/3 applied.

These patches will need to be applied on top of my recent rework of
TM: http://patchwork.ozlabs.org/patch/666094/
I have pushed a branch to github to help with reviews:
https://github.com/cyrilbur-ibm/linux/tree/tm_lazy_v1

Changes since RFC:
Fixed my unability to use & and | correctly.
- Spotted by Laurent Dufour, thanks
Dropped the selftest patch as it was merged as part of a previous
series

Cyril Bur (2):
powerpc: tm: Add TM Unavailable Exception
powerpc: tm: Enable transactional memory (TM) lazily for userspace

 arch/powerpc/include/asm/processor.h |  1 +
 arch/powerpc/kernel/process.c        | 28 +++++++++++++++++++++++-----
 arch/powerpc/kernel/traps.c          | 34 ++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 5 deletions(-)

2.9.3