ARM: boot: mxs: Add On-Chip RAM
Get series with b4
b4 am 20161021150336.GJ30578@tigerVersions newest first
- v1 Latest0 of 4 patches 0 repliesNew
Patches in v1 No applies recorded yet
None of the 4 patches the cover letter announces are in this archive.
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.
Cover letter [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
Quoted 13 lines · Stefan Wahren
Am 21.10.2016 um 15:53 schrieb Shawn Guo:
Quoted 11 lines · Stefan Wahren
Quoted 8 lines
The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary for suspend to RAM and standby mode. But before we need to remove the fake reg properties of all internal bus nodes as discussed in this thread [1].
This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
Removeskeleton.dtsiinclusion" [2].The page cannot be reached. I would like to understand the background for this change.
Quoted 7 lines
Strange, because i don't have any problems while clicking on the URL.
It's an older discussion on the devicetree / kernel newbie mailing list with subject "strange dtc errors after adding sram node". Arnd suggested in the discussion to remove the reg property from the ahb node.
Please try this one: http://www.spinics.net/lists/newbies/msg57652.html
If you go through 'Table 4-1. Address Map for i.MX28' of MCIMX28RM, you should be able to find there are 3 AHB buses: ahb at 0, ahb at 80080000 and ahb at c0000000. The ocram goes to ahb at 0. The following change should be the right one for ocram addition.
arch/arm/boot/dts/imx28.dtsi +13 -0
@@ -47,6 +47,19 @@ }; }; + ahb at 0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x80000000>; + ranges; + + ocram: sram at 0 { + compatible = "mmio-sram"; + reg = <0x0 0x20000>; + }; + }; + apb at 80000000 { compatible = "simple-bus"; #address-cells = <1>;