clk: stm32f4: don't assume 48MHz clock is derived from primary PLL
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- v1 Latest1 patch 0 repliesNew
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| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/1 | clk: stm32f4: don't assume 48MHz clock is derived from primary PLL | +0 | 1 reply |
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