clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
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- v1 Latest3 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/3 | clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks | +0 | 0 replies | |
| 2/3 | zte: clk: pd_bit is not 0 on zx296718 | +0 | 0 replies | |
| 3/3 | clk: zte: add pll_vga clock for zx296718 | +0 | 0 replies |
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