idle performance improvements
Status from this message: Applied to powerpc next, thanks.
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v3 Latest posting 2/213 patches 18 repliesApplied
- v3 posting 1/20 of 13 patches 0 repliesSuperseded
- v2 posting 2/214 patches 26 repliesSuperseded
Earlier versions · 2
| Version | Posted | Patches | Replies | Status |
|---|---|---|---|---|
| v2 posting 1/2 | 0 of 14 patches | 2 replies | Superseded | |
| v1 | 14 patches | 0 replies | Superseded |
Patches in v3 posting 2/2 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/13 | powerpc/64s: idle move soft interrupt mask logic into C codearch/ arch/ arch/ +6 more | +128 | 1 reply | |
| 2/13 | powerpc/64s: idle hotplug lazy-irq simplificationarch/ arch/ | +29 | 1 reply | |
| 3/13 | powerpc/64s: idle process interrupts from system reset wakeuparch/ arch/ arch/ | +39 | 3 replies | |
| 4/13 | powerpc/64s: msgclr when handling doorbell exceptionsarch/ arch/ arch/ +1 more | +38 | 1 reply | |
| 5/13 | powerpc/64s: interrupt replay balance the return branch predictorarch/ | +7 | 1 reply | |
| 6/13 | powerpc/64s: idle branch to handler with virtual mode offsetarch/ arch/ | +17 | 1 reply | |
| 7/13 | powerpc/64s: idle avoid SRR usage in idle sleep/wake pathsarch/ arch/ arch/ | +33 | 2 replies | |
| 8/13 | powerpc/64s: idle hmi wakeup is unlikelyarch/ | +1 | 1 reply | |
| 9/13 | powerpc/64s: cpuidle set polling before enabling irqsdrivers/ drivers/ | +5 | 3 replies | |
| 10/13 | powerpc/64s: cpuidle read mostly for common globalsdrivers/ drivers/ | +9 | 0 replies | |
| 11/13 | powerpc/64s: cpuidle no memory barrier after break from idledrivers/ drivers/ | +18 | 0 replies | |
| 12/13 | powerpc/64: runlatch CTRL[RUN] set optimisationarch/ | +2 | 3 replies | |
| 13/13 | powerpc/64s: idle runlatch switch is done with MSR[EE]=0arch/ | +6 | 1 reply |
Reviews trailers per patch
9 of 13 patches have a Reviewed-by or Acked-by.
| Patch | Gautham R. Shenoy | Vaidyanathan Srinivasan |
|---|---|---|
| 1/13 | R-b | |
| 2/13 | ||
| 3/13 | ||
| 4/13 | R-b | |
| 5/13 | R-b | |
| 6/13 | ||
| 7/13 | ||
| 8/13 | R-b | |
| 9/13 | R-b | |
| 10/13 | R-b | R-b |
| 11/13 | R-b | |
| 12/13 | R-b | |
| 13/13 | A-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH 00/13 v3] idle performance improvements
Since last time, I accounted for the various comments in reviews, most importantly fixed the miscalculation of SRR1 bit for the wakeup-interrupt. Verified it does the right thing and replays the right wakeup interrupt (e.g., decrementer) from __replay_interrupt stepping through the instructions in the simulator.
I've found that performance testing is a little difficult because the ping-pong test cases must sometimes get into synchronization and run concurrently without sleeping. Looking at context switch rates in vmstat, I run the context-switch ping-poing test with snooze idle disabled on a POWER8, and the numbers before and after this series are:
different thread different core vanilla 600K/s 470K/s patched 780K/s 550K/s
(these are 2x what's reported by context_switch selftest because each step switches to and from idle thread)
It's still not a perfect measurement because if there is some unwanted concurrency happening then you can get different amount of userspace work per context switch, but there seems to be a decent speedup here.
Thanks,
Nick
Nicholas Piggin (13):
powerpc/64s: idle move soft interrupt mask logic into C code powerpc/64s: idle hotplug lazy-irq simplification powerpc/64s: idle process interrupts from system reset wakeup powerpc/64s: msgclr when handling doorbell exceptions powerpc/64s: interrupt replay balance the return branch predictor powerpc/64s: idle branch to handler with virtual mode offset powerpc/64s: idle avoid SRR usage in idle sleep/wake paths powerpc/64s: idle hmi wakeup is unlikely
powerpc/64s: cpuidle set polling before enabling irqs powerpc/64s: cpuidle read mostly for common globals powerpc/64s: cpuidle no memory barrier after break from idle powerpc/64: runlatch CTRL[RUN] set optimisation powerpc/64s: idle runlatch switch is done with MSR[EE]=0
arch/powerpc/include/asm/dbell.h | 13 +++ arch/powerpc/include/asm/exception-64s.h | 13 +++ arch/powerpc/include/asm/hw_irq.h | 5 ++ arch/powerpc/include/asm/machdep.h | 1 + arch/powerpc/include/asm/ppc-opcode.h | 3 + arch/powerpc/include/asm/processor.h | 10 +-- arch/powerpc/kernel/asm-offsets.c | 1 + arch/powerpc/kernel/exceptions-64s.S | 38 +++++++-- arch/powerpc/kernel/idle_book3s.S | 135 +++++++++---------------------- arch/powerpc/kernel/irq.c | 62 +++++++++++++- arch/powerpc/kernel/process.c | 12 +-- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 8 +- arch/powerpc/platforms/powernv/idle.c | 88 ++++++++++++++++++-- arch/powerpc/platforms/powernv/smp.c | 31 ++++--- arch/powerpc/platforms/powernv/subcore.c | 3 +- drivers/cpuidle/cpuidle-powernv.c | 37 +++++---- drivers/cpuidle/cpuidle-pseries.c | 22 +++-- 17 files changed, 315 insertions(+), 167 deletions(-)
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2.11.0