clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
Get series with b4
b4 am [email protected]Versions newest first
- v1 Latest1 patch 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/1 | clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' | +0 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.