CPU clock changes for Tegra20/30
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- v1 Latest3 patches 5 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/3 | clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30drivers/ drivers/ drivers/ +1 more | +28 | 2 replies | |
| 2/3 | clk: tegra: Add more rates to Tegra30 PLLX frequency tabledrivers/ | +42 | 2 replies | |
| 3/3 | clk: tegra: Poll PLLX lock-status on resume from suspend on Tegra20/30drivers/ drivers/ | +86 | 0 replies |
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Cover letter [PATCH v1 0/3] CPU clock changes for Tegra20/30
Hello,
This series is a prerequisite for the CPUFREQ driver patches, it can be applied separately. CPUFREQ will be supported on Tegra30 once this and the CPUFREQ patch-series will be applied.
Dmitry Osipenko (3):
clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30
clk: tegra: Add more rates to Tegra30 PLLX frequency table
clk: tegra: Poll PLLX lock-status on resume from suspend on Tegra20/30
drivers/clk/tegra/clk-super.c | 16 +++- drivers/clk/tegra/clk-tegra20.c | 51 ++++++++++-- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/tegra/clk-tegra30.c | 131 +++++++++++++++++++++---------- drivers/clk/tegra/clk.h | 9 ++- 5 files changed, 156 insertions(+), 53 deletions(-)
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2.18.0