More fully implement ARM PMUv3
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- v6 Latest14 patches 39 repliesIn review
Patches in v6 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/14 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IOtarget/ | +4 | 1 reply | |
| 2/14 | target/arm: Mask PMOVSR writes based on supported counterstarget/ | +1 | 1 reply | |
| 3/14 | migration: Add post_save function to VMStateDescriptiondocs/ include/ migration/ | +17 | 8 replies | |
| 4/14 | target/arm: Swap PMU values before/after migrationstarget/ target/ | +23 | 2 replies | |
| 5/14 | target/arm: Reorganize PMCCNTR accessestarget/ target/ target/ | +73 | 5 replies | |
| 6/14 | target/arm: Filter cycle counter based on PMCCFILTR_EL0target/ target/ target/ +1 more | +137 | 2 replies | |
| 7/14 | target/arm: Allow AArch32 access for PMCCFILTRtarget/ | +26 | 1 reply | |
| 8/14 | target/arm: Implement PMOVSSETtarget/ | +28 | 1 reply | |
| 9/14 | target/arm: Add array for supported PMU events, generate PMCEID[01]target/ target/ target/ +1 more | +65 | 2 replies | |
| 10/14 | target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPERtarget/ target/ | +282 | 1 reply | |
| 11/14 | target/arm: PMU: Add instruction and cycle eventstarget/ | +44 | 4 replies | |
| 12/14 | target/arm: PMU: Set PMCR.N to 4target/ | +4 | 7 replies | |
| 13/14 | target/arm: Implement PMSWINCtarget/ | +37 | 1 reply | |
| 14/14 | target/arm: Send interrupts on PMU counter overflowtarget/ target/ target/ | +138 | 0 replies |
Reviews trailers per patch
8 of 14 patches have a Reviewed-by or Acked-by.
| Patch | Peter Maydell | Richard Henderson |
|---|---|---|
| 1/14 | R-b | |
| 2/14 | R-b | |
| 3/14 | ||
| 4/14 | ||
| 5/14 | ||
| 6/14 | R-b | R-b |
| 7/14 | R-b | R-b |
| 8/14 | R-b | |
| 9/14 | ||
| 10/14 | R-b | |
| 11/14 | R-b | |
| 12/14 | ||
| 13/14 | R-b | |
| 14/14 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [Qemu-arm] [PATCH v6 00/14] More fully implement ARM PMUv3
The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events, filter them based on execution mode, and/or be notified on counter overflow. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events.
Since v5 [1] I have:
* Taken a first pass at addressing migration
* Restructured the list of supported events, and ensured they're all initialized
* Fixed aliasing for PMOVSSET
* Added ARM_CP_IO for PMINTENCLR and PMINTENCLR_EL1
* Addressed a few non-code issues (comment style, patch staging, spelling, etc.)
[1] - https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06830.html
Aaron Lindsay (14):
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly
doing IO
target/arm: Mask PMOVSR writes based on supported counters
migration: Add post_save function to VMStateDescription target/arm: Swap PMU values before/after migrations target/arm: Reorganize PMCCNTR accesses
target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Implement PMOVSSET
target/arm: Add array for supported PMU events, generate PMCEID[01] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4
target/arm: Implement PMSWINC
target/arm: Send interrupts on PMU counter overflow
docs/devel/migration.rst | 9 +- include/migration/vmstate.h | 1 + migration/vmstate.c | 10 +- target/arm/cpu.c | 28 +- target/arm/cpu.h | 68 +++- target/arm/cpu64.c | 2 - target/arm/helper.c | 781 ++++++++++++++++++++++++++++++++---- target/arm/machine.c | 19 + 8 files changed, 817 insertions(+), 101 deletions(-)
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