clk: samsung: exynos5420: add VPLL rate table for g3d clock
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- v1 Latest3 patches 4 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/3 | clk: samsung: exynos5420: add VPLL rate table for g3d clockdrivers/ | +13 | 2 replies | |
| 2/3 | clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_sclk_vplldrivers/ | +2 | 0 replies | |
| 3/3 | ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoCarch/ arch/ | +56 | 2 replies |
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