Relax sanity checking for mismatched AArch32 EL1
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b4 am [email protected]Versions newest first · linked by author and title
- v2 Latest8 patches 1 replyIn review
- v18 patches 23 repliesSuperseded
Patches in v2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/8 | arm64: cpufeature: Relax check for IESB supportarch/ | +1 | 0 replies | |
| 2/8 | arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1arch/ arch/ | +43 | 0 replies | |
| 3/8 | arm64: cpufeature: Add CPU capability for AArch32 EL1 supportarch/ arch/ arch/ +1 more | +17 | 0 replies | |
| 4/8 | arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0()arch/ | +1 | 0 replies | |
| 5/8 | arm64: cpufeature: Factor out checking of AArch32 featuresarch/ | +65 | 0 replies | |
| 6/8 | arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit onlyarch/ arch/ | +39 | 0 replies | |
| 7/8 | arm64: cpufeature: Relax checks for AArch32 support at EL[0-2]arch/ | +3 | 0 replies | |
| 8/8 | arm64: cpufeature: Add an overview comment for the cpufeature frameworkarch/ | +50 | 1 reply |
Reviews trailers per patch
All 8 patches have a Reviewed-by or Acked-by.
| Patch | Suzuki K Poulose | Sai Prakash Ranjan | Marc Zyngier |
|---|---|---|---|
| 1/8 | R-b | ||
| 2/8 | R-b | T-b | |
| 3/8 | R-b | T-b | A-b |
| 4/8 | R-b | T-b | |
| 5/8 | R-b | T-b | |
| 6/8 | R-b | T-b | |
| 7/8 | R-b | T-b | |
| 8/8 | R-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.
Cover letter [PATCH v2 0/8] Relax sanity checking for mismatched AArch32 EL1
Hi folks,
This is version two of the patches I previously posted here:
https://lore.kernel.org/lkml/[email protected]/
Changes since v1 include:
* Typo fixes
* Added comment to update_32bit_cpu_features() callsite regarding sanitisation
* Extended comment in final patch to mention KVM
* Add acks/tested-bys
Cheers,
Will
--->8
Sai Prakash Ranjan (1):
arm64: cpufeature: Relax check for IESB support
Will Deacon (7):
arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1
arm64: cpufeature: Add CPU capability for AArch32 EL1 support
arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0()
arm64: cpufeature: Factor out checking of AArch32 features
arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only
arm64: cpufeature: Relax checks for AArch32 support at EL[0-2]
arm64: cpufeature: Add an overview comment for the cpufeature
framework
arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cpufeature.h | 7 + arch/arm64/include/asm/sysreg.h | 18 ++ arch/arm64/kernel/cpufeature.c | 247 +++++++++++++++++++++------- arch/arm64/kvm/reset.c | 12 +- 5 files changed, 217 insertions(+), 70 deletions(-)
Signature · 1 line
2.26.1.301.g55bc3eb7cb9-goog