JH7100 Audio Clocks
Status from this message: Applied to clk-next
Get series with b4
b4 am [email protected]Versions newest first
Patches in v1 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/7 | clk: starfive: jh7100: Don't round divisor up twicedrivers/ | +3 | 1 reply | |
| 2/7 | clk: starfive: jh7100: Handle audio_div clock properlydrivers/ | +67 | 1 reply | |
| 3/7 | dt-bindings: clock: Add JH7100 audio clock definitionsinclude/ | +41 | 2 replies | |
| 4/7 | dt-bindings: clock: Add starfive,jh7100-audclk bindingsDocumentation/ | +57 | 2 replies | |
| 5/7 | clk: starfive: jh7100: Make hw clock implementation reusabledrivers/ drivers/ | +104 | 1 reply | |
| 6/7 | clk: starfive: jh7100: Support more clock typesdrivers/ drivers/ | +41 | 1 reply | |
| 7/7 | clk: starfive: Add JH7100 audio clock driverMAINTAINERS drivers/ drivers/ +1 more | +183 | 1 reply |
Reviews trailers per patch
2 of 7 patches have a Reviewed-by or Acked-by.
| Patch | Rob Herring |
|---|---|
| 1/7 | |
| 2/7 | |
| 3/7 | A-b |
| 4/7 | R-b |
| 5/7 | |
| 6/7 | |
| 7/7 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v1 0/7] JH7100 Audio Clocks
This series add support for the audio clocks on the StarFive JH7100 RISC-V SoC, although the first two patches are fixes to the original addition of the basic clock driver. At least the first fix may be considered for 5.17.
It turns out the SoC has several memory ranges for different clocks, but they all share the layout of the control registers. This could be modelled in 3 ways:
1) Model all the clocks as a single peripheral with multiple memory ranges and have a single driver for them all.
2) Model each memory range as different, but related peripherals with a single driver handling all of them.
3) Model each memory range as different peripherals with separate drivers that can share most code.
Although the first option would require less code this series implements the 3rd option. The basic clock driver has to be built-in to boot the SoC, so separate drivers for the other registers means less code needs to be built-in and can be left as loadable modules.
Emil Renner Berthing (7):
clk: starfive: jh7100: Don't round divisor up twice
clk: starfive: jh7100: Handle audio_div clock properly
dt-bindings: clock: Add JH7100 audio clock definitions
dt-bindings: clock: Add starfive,jh7100-audclk bindings
clk: starfive: jh7100: Make hw clock implementation reusable
clk: starfive: jh7100: Support more clock types
clk: starfive: Add JH7100 audio clock driver
.../clock/starfive,jh7100-audclk.yaml | 57 ++++++ MAINTAINERS | 8 +- drivers/clk/starfive/Kconfig | 8 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jh7100-audio.c | 170 +++++++++++++++++ drivers/clk/starfive/clk-starfive-jh7100.c | 176 +++++++++--------- drivers/clk/starfive/clk-starfive-jh7100.h | 112 +++++++++++ .../dt-bindings/clock/starfive-jh7100-audio.h | 41 ++++ 8 files changed, 482 insertions(+), 91 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jh7100-audio.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h create mode 100644 include/dt-bindings/clock/starfive-jh7100-audio.h
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