OpenRISC floating point context support

This series adds support for storing and restoring the OpenRISC floating point context as well as user space API's and regsets.

To support these patches an architecture change had to be made. The OpenRISC fpu status and control register FPCSR is now read/writeable by user space as of architecture spec revision 1.4:

- https://openrisc.io/revisions/r1.4

Previous to this FPCSR reads and writes from user-mode would just be ignored, reads and writes to non permissioned special purpose registers (SPR's) are no-ops.

The patch is split into 3 main parts, the first patch being a cleanup to handling exceptions noticed while working on this.

1. Add support to context saving and switching
2. Add support for SIGFPE and sigcontext
3. Add regset for ptrace register reading/writing

The series has been tested with the glibc test suite and all math tests are passing. Patched projects include:

- GCC - patches upstream to fix issue with resetting exceptions in libgcc
- glibc - https://github.com/stffrdhrn/or1k-glibc/commits/or1k-hard-float
- qemu - https://github.com/stffrdhrn/qemu/commits/or1k-user-fpcsr

I have not worked on binutils-gdb patches yet.

Stafford Horne (4):
openrisc: Properly store r31 to pt_regs on unhandled exceptions
openrisc: Support storing and restoring fpu state
openrisc: Support floating point user api
openrisc: Add floating point regset

 arch/openrisc/include/asm/ptrace.h          |  4 +--
 arch/openrisc/include/uapi/asm/elf.h        |  3 +-
 arch/openrisc/include/uapi/asm/ptrace.h     |  4 +++
 arch/openrisc/include/uapi/asm/sigcontext.h |  1 +
 arch/openrisc/kernel/entry.S                | 31 +++++++++++++----
 arch/openrisc/kernel/head.S                 |  4 +--
 arch/openrisc/kernel/ptrace.c               | 37 +++++++++++++++++++++
 arch/openrisc/kernel/signal.c               |  2 ++
 arch/openrisc/kernel/traps.c                | 27 +++++++++++++--
 9 files changed, 99 insertions(+), 14 deletions(-)

2.39.1