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Add Sipeed Lichee Pi 4A RISC-V board support

Jisheng Zhang linux-devicetree linux-riscv lkml 3 versions – Applied

Status from this message: Applied to riscv-dt-for-next, thanks!

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b4 am [email protected]

Versions newest first · linked by author and title

  1. v3 Latest8 patches 29 repliesApplied
  2. v29 patches 20 repliesSuperseded
  3. v15 patches 31 repliesSuperseded

Changes in v3 from the cover letter

- remove thead cpu-rst dt-binding doc and its DT node from th1520.dtsi
- collect Reviewed-by and Acked-by tags
- update uart reg size as suggested by Yixun
- Add Guo Ren and Fu Wei as THEAD SoCs Maintainers

Patches in v3 Applied

#Subject and filesSizeRepliesApplied
1/8dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLICDocumentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml+1 -00 replies
2/8dt-bindings: timer: Add T-HEAD TH1520 clintDocumentation/devicetree/bindings/timer/sifive,clint.yaml+1 -00 replies
3/8dt-bindings: riscv: Add T-HEAD TH1520 board compatiblesDocumentation/devicetree/bindings/riscv/thead.yaml+29 -00 replies
4/8riscv: Add the T-HEAD SoC family Kconfig optionarch/riscv/Kconfig.socs+6 -00 replies
5/8riscv: dts: add initial T-HEAD TH1520 SoC device treearch/riscv/boot/dts/thead/th1520.dtsi+422 -00 replies
6/8riscv: dts: thead: add sipeed Lichee Pi 4A board device treearch/riscv/boot/dts/Makefile arch/riscv/boot/dts/thead/Makefile arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +1 more+73 -00 replies
7/8MAINTAINERS: add entry for T-HEAD RISC-V SoCMAINTAINERS+8 -00 replies
8/8riscv: defconfig: enable T-HEAD SoCarch/riscv/configs/defconfig+1 -00 replies

Reviews trailers per patch

5 of 8 patches have a Reviewed-by or Acked-by.

PatchConor DooleyGuo RenPalmer Dabbelt
1/8R-b R-b
2/8R-b
3/8
4/8R-b
5/8
6/8
7/8A-b
8/8R-b A-b A-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.

Read the v3 thread

Cover letter [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic shell.

NOTE: the thead cpu reset dt-binding and DT node are removed in v3. This makes secondary CPUs unable to be online. However, minimal th1520 support is better than nothing. And the community has been working on and will work on the cpu reset dt-binding, for example, Conor, Guo and Jessica are discussing about it, I have seen valuable comments and inputs from them. I believe we can add back cpu reset in next development window.

Thanks

Since v2:
- remove thead cpu-rst dt-binding doc and its DT node from th1520.dtsi
- collect Reviewed-by and Acked-by tags
- update uart reg size as suggested by Yixun
- Add Guo Ren and Fu Wei as THEAD SoCs Maintainers

Since v1:
- add missing plic, clint, th1520 itself dt-bindings
- use c900-plic
- s/light/th1520
- add dt-binding for T-HEAD CPU reset
- enable ARCH_THEAD in defconfig
- fix all dtbs_check error/warning except the CPU RESET, see above.

Jisheng Zhang (8):
dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
dt-bindings: timer: Add T-HEAD TH1520 clint
dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
riscv: Add the T-HEAD SoC family Kconfig option
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: defconfig: enable T-HEAD SoC

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/thead.yaml      |  29 ++
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |   8 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/thead/Makefile            |   2 +
 .../dts/thead/th1520-lichee-module-4a.dtsi    |  38 ++
 .../boot/dts/thead/th1520-lichee-pi-4a.dts    |  32 ++
 arch/riscv/boot/dts/thead/th1520.dtsi         | 422 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 11 files changed, 541 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
 create mode 100644 arch/riscv/boot/dts/thead/Makefile
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
 create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
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