arm64: Add support for LPA2 and WXN at stage 1
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- v8 Latest43 patches 25 repliesIn review
- v750 patches 1 replySuperseded
Changes in v8 from the cover letter
- rebase onto arm64/reorg-va-space and drop the patches that were merged
- bring back the KVM change to rely on vabits_actual to decide at which level a walk of the user space page tables should start
Patches in v8 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/43 | arm64: kernel: Manage absolute relocations in code built under pi/arch/ arch/ arch/ | +155 | 0 replies | |
| 2/43 | arm64: kernel: Don't rely on objcopy to make code under pi/ __initarch/ arch/ | +13 | 0 replies | |
| 3/43 | arm64: head: move relocation handling to C codearch/ arch/ arch/ +2 more | +82 | 0 replies | |
| 4/43 | arm64: idreg-override: Move to early mini C runtimearch/ arch/ arch/ +2 more | +30 | 0 replies | |
| 5/43 | arm64: kernel: Remove early fdt remap codearch/ arch/ | +0 | 0 replies | |
| 6/43 | arm64: head: Clear BSS and the kernel page tables in one goarch/ arch/ | +14 | 0 replies | |
| 7/43 | arm64: Move feature overrides into the BSS sectionarch/ | +7 | 0 replies | |
| 8/43 | arm64: head: Run feature override detection before mapping the kernelarch/ arch/ | +10 | 0 replies | |
| 9/43 | arm64: head: move dynamic shadow call stack patching into early C runtimearch/ arch/ arch/ +3 more | +27 | 0 replies | |
| 10/43 | arm64: cpufeature: Add helper to test for CPU feature overridesarch/ arch/ | +40 | 0 replies | |
| 11/43 | arm64: kaslr: Use feature override instead of parsing the cmdline againarch/ arch/ arch/ | +7 | 0 replies | |
| 12/43 | arm64: idreg-override: Create a pseudo feature for rodata=offarch/ arch/ | +3 | 0 replies | |
| 13/43 | arm64: Add helpers to probe local CPU for PAC and BTI supportarch/ | +32 | 0 replies | |
| 14/43 | arm64: head: allocate more pages for the kernel mappingarch/ | +10 | 0 replies | |
| 15/43 | arm64: head: move memstart_offset_seed handling to C codearch/ arch/ arch/ | +5 | 0 replies | |
| 16/43 | arm64: mm: Make kaslr_requires_kpti() a static inlinearch/ arch/ arch/ | +39 | 0 replies | |
| 17/43 | arm64: mmu: Make __cpu_replace_ttbr1() out of linearch/ arch/ | +33 | 0 replies | |
| 18/43 | arm64: head: Move early kernel mapping routines into C codearch/ arch/ arch/ +12 more | +315 | 0 replies | |
| 19/43 | arm64: mm: Use 48-bit virtual addressing for the permanent ID maparch/ arch/ arch/ +2 more | +32 | 0 replies | |
| 20/43 | arm64: pgtable: Decouple PGDIR size macros from PGD/PUD/PMD levelsarch/ | +19 | 0 replies | |
| 21/43 | arm64: kernel: Create initial ID map from C codearch/ arch/ arch/ +8 more | +88 | 0 replies | |
| 22/43 | arm64: mm: avoid fixmap for early swapper_pg_dir updatesarch/ | +15 | 0 replies | |
| 23/43 | arm64: mm: omit redundant remap of kernel imagearch/ arch/ arch/ +5 more | +21 | 0 replies | |
| 24/43 | arm64: Revert "mm: provide idmap pointer to cpu_replace_ttbr1()"arch/ arch/ arch/ | +10 | 0 replies | |
| 25/43 | arm64: mm: Handle LVA support as a CPU featurearch/ arch/ arch/ +7 more | +49 | 0 replies | |
| 26/43 | arm64: mm: Add feature override support for LVAarch/ arch/ arch/ +2 more | +53 | 0 replies | |
| 27/43 | arm64: Avoid #define'ing PTE_MAYBE_NG to 0x0 for asm usearch/ arch/ | +13 | 0 replies | |
| 28/43 | arm64: Add ESR decoding for exceptions involving translation level -1arch/ arch/ arch/ | +18 | 0 replies | |
| 29/43 | arm64: mm: Wire up TCR.DS bit to PTE shareability fieldsarch/ arch/ arch/ +2 more | +25 | 0 replies | |
| 30/43 | arm64: mm: Add LPA2 support to phys<->pte conversion routinesarch/ arch/ arch/ +1 more | +20 | 0 replies | |
| 31/43 | arm64: mm: Add definitions to support 5 levels of pagingarch/ arch/ arch/ +3 more | +188 | 0 replies | |
| 32/43 | arm64: mm: add LPA2 and 5 level paging support to G-to-nG conversionarch/ arch/ | +66 | 0 replies | |
| 33/43 | arm64: Enable LPA2 at boot if supported by the systemarch/ arch/ arch/ +8 more | +124 | 4 replies | |
| 34/43 | arm64: mm: Add 5 level paging support to fixmap and swapper handlingarch/ arch/ arch/ +1 more | +85 | 0 replies | |
| 35/43 | arm64: kasan: Reduce minimum shadow alignment and enable 5 level pagingarch/ arch/ | +130 | 0 replies | |
| 36/43 | arm64: mm: Add support for folding PUDs at runtimearch/ arch/ arch/ +3 more | +95 | 13 replies | |
| 37/43 | arm64: ptdump: Disregard unaddressable VA spacearch/ | +2 | 0 replies | |
| 38/43 | arm64: ptdump: Deal with translation levels folded at runtimearch/ | +12 | 0 replies | |
| 39/43 | arm64: kvm: avoid CONFIG_PGTABLE_LEVELS for runtime levelsarch/ | +1 | 0 replies | |
| 40/43 | arm64: Enable 52-bit virtual addressing for 4k and 16k granule configsarch/ arch/ | +28 | 0 replies | |
| 41/43 | arm64: defconfig: Enable LPA2 supportarch/ arch/ | +1 | 0 replies | |
| 42/43 | mm: add arch hook to validate mmap() prot flagsinclude/ mm/ | +18 | 5 replies | |
| 43/43 | arm64: mm: add support for WXN memory translation attributearch/ arch/ arch/ +4 more | +116 | 0 replies |
Reviews trailers per patch
3 of 43 patches have a Reviewed-by or Acked-by.
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Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.
Cover letter [PATCH v8 00/43] arm64: Add support for LPA2 and WXN at stage 1
From: Ard Biesheuvel <[email protected]>
This v8 covers the remaining changes that implement support for LPA2 and WXN at stage 1, now that some of the prerequisites are in place.
v4: https://lore.kernel.org/r/[email protected]/
v5: https://lore.kernel.org/r/[email protected]/
v6: https://lore.kernel.org/r/[email protected]/
v7: https://lore.kernel.org/r/20240123145258.1462979-52-ardb%2Bgit%40google.com/
-%-
Changes in v8:
- rebase onto arm64/reorg-va-space and drop the patches that were merged
- bring back the KVM change to rely on vabits_actual to decide at which level a walk of the user space page tables should start
Changes in v7:
- rebase onto v6.8-rc1 which includes some patches of the previous revision, and includes the KVM changes for LPA2
The first ~30 patches rework the early init code, reimplementing most of the page table and relocation handling in C code. There are several reasons why this is needed:
- we generally prefer C code over asm for these things, and the macros that currently exist in head.S for creating the kernel page tables are a good example why;
- we no longer need to create the kernel mapping in two passes, which means we can remove the logic that copies parts of the fixmap and the KAsan shadow from one set of page tables to the other; this is especially advantageous for KAsan with LPA2, which needs more elaborate shadow handling across multiple levels, since the KAsan region cannot be placed on exact pgd_t boundaries in that case;
- we can read the ID registers and parse command line overrides before creating the page tables, which simplifies the LPA2 case, as flicking the global TCR_EL1.DS bit at a later stage would require elaborate repainting of all page table descriptors, some of which with the MMU disabled;
- we can use more elaborate logic to create the mappings, which means we can use more precise mappings for code and data sections even when using 2 MiB granularity, and this is a prerequisite for running with WXN.
As part of the ID map changes, we decouple the ID map size from the kernel VA size, and switch to a 48-bit VA map for all configurations.
The next ~10 patches rework the existing LVA support as a CPU feature, which simplifies some code and gets rid of the vabits_actual variable. Then, LPA2 support is implemented in the same vein. This requires adding support for 5 level paging as well, given that LPA2 introduces a new paging level '-1' when using 4k pages.
Combined with the vmemmap changes at the start of the series, the resulting LPA2/4k pages configuration will have the exact same VA space layout as the ordinary 4k/4 levels configuration, and so LPA2 support can reasonably be enabled by default, as the fallback is seamless on non-LPA2 hardware.
In the 16k/LPA2 case, the fallback also reduces the number of paging levels, resulting in a 47-bit VA space. This is based on the assumption that hybrid LPA2/non-LPA2 16k pages kernels in production use would prefer not to take the performance hit of 4 level paging to gain only a single additional bit of VA space. (Note that generic Android kernels use only 3 levels of paging today.) Bespoke 16k configurations can still configure 48-bit virtual addressing as before.
Finally, enable support for running with the WXN control enabled. This was previously part of a separate series, but given that the delta is tiny, it is included here as well.
Ard Biesheuvel (43):
arm64: kernel: Manage absolute relocations in code built under pi/
arm64: kernel: Don't rely on objcopy to make code under pi/ __init
arm64: head: move relocation handling to C code
arm64: idreg-override: Move to early mini C runtime
arm64: kernel: Remove early fdt remap code
arm64: head: Clear BSS and the kernel page tables in one go
arm64: Move feature overrides into the BSS section
arm64: head: Run feature override detection before mapping the kernel
arm64: head: move dynamic shadow call stack patching into early C
runtime
arm64: cpufeature: Add helper to test for CPU feature overrides
arm64: kaslr: Use feature override instead of parsing the cmdline
again
arm64: idreg-override: Create a pseudo feature for rodata=off
arm64: Add helpers to probe local CPU for PAC and BTI support
arm64: head: allocate more pages for the kernel mapping
arm64: head: move memstart_offset_seed handling to C code
arm64: mm: Make kaslr_requires_kpti() a static inline
arm64: mmu: Make __cpu_replace_ttbr1() out of line
arm64: head: Move early kernel mapping routines into C code
arm64: mm: Use 48-bit virtual addressing for the permanent ID map
arm64: pgtable: Decouple PGDIR size macros from PGD/PUD/PMD levels
arm64: kernel: Create initial ID map from C code
arm64: mm: avoid fixmap for early swapper_pg_dir updates
arm64: mm: omit redundant remap of kernel image
arm64: Revert "mm: provide idmap pointer to cpu_replace_ttbr1()"
arm64: mm: Handle LVA support as a CPU feature
arm64: mm: Add feature override support for LVA
arm64: Avoid #define'ing PTE_MAYBE_NG to 0x0 for asm use
arm64: Add ESR decoding for exceptions involving translation level -1
arm64: mm: Wire up TCR.DS bit to PTE shareability fields
arm64: mm: Add LPA2 support to phys<->pte conversion routines
arm64: mm: Add definitions to support 5 levels of paging
arm64: mm: add LPA2 and 5 level paging support to G-to-nG conversion
arm64: Enable LPA2 at boot if supported by the system
arm64: mm: Add 5 level paging support to fixmap and swapper handling
arm64: kasan: Reduce minimum shadow alignment and enable 5 level
paging
arm64: mm: Add support for folding PUDs at runtime
arm64: ptdump: Disregard unaddressable VA space
arm64: ptdump: Deal with translation levels folded at runtime
arm64: kvm: avoid CONFIG_PGTABLE_LEVELS for runtime levels
arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs
arm64: defconfig: Enable LPA2 support
mm: add arch hook to validate mmap() prot flags
arm64: mm: add support for WXN memory translation attribute
arch/arm64/Kconfig | 38 +-
arch/arm64/configs/defconfig | 1 -
arch/arm64/include/asm/archrandom.h | 2 -
arch/arm64/include/asm/assembler.h | 55 +--
arch/arm64/include/asm/cpufeature.h | 116 +++++
arch/arm64/include/asm/esr.h | 13 +-
arch/arm64/include/asm/fixmap.h | 2 +-
arch/arm64/include/asm/kasan.h | 2 -
arch/arm64/include/asm/kernel-pgtable.h | 103 ++---
arch/arm64/include/asm/kvm_emulate.h | 10 +-
arch/arm64/include/asm/memory.h | 17 +-
arch/arm64/include/asm/mman.h | 36 ++
arch/arm64/include/asm/mmu.h | 40 +-
arch/arm64/include/asm/mmu_context.h | 83 ++--
arch/arm64/include/asm/pgalloc.h | 53 ++-
arch/arm64/include/asm/pgtable-hwdef.h | 33 +-
arch/arm64/include/asm/pgtable-prot.h | 20 +-
arch/arm64/include/asm/pgtable-types.h | 6 +
arch/arm64/include/asm/pgtable.h | 219 ++++++++-
arch/arm64/include/asm/scs.h | 36 +-
arch/arm64/include/asm/setup.h | 3 -
arch/arm64/include/asm/tlb.h | 3 +
arch/arm64/kernel/Makefile | 13 +-
arch/arm64/kernel/cpufeature.c | 111 +++--
arch/arm64/kernel/head.S | 463 ++------------------
arch/arm64/kernel/image-vars.h | 35 +-
arch/arm64/kernel/kaslr.c | 4 +-
arch/arm64/kernel/module.c | 2 +-
arch/arm64/kernel/pi/Makefile | 27 +-
arch/arm64/kernel/{ => pi}/idreg-override.c | 80 ++--
arch/arm64/kernel/pi/kaslr_early.c | 67 +--
arch/arm64/kernel/pi/map_kernel.c | 276 ++++++++++++
arch/arm64/kernel/pi/map_range.c | 105 +++++
arch/arm64/kernel/{ => pi}/patch-scs.c | 36 +-
arch/arm64/kernel/pi/pi.h | 36 ++
arch/arm64/kernel/pi/relacheck.c | 130 ++++++
arch/arm64/kernel/pi/relocate.c | 64 +++
arch/arm64/kernel/setup.c | 22 -
arch/arm64/kernel/sleep.S | 3 -
arch/arm64/kernel/vmlinux.lds.S | 17 +-
arch/arm64/kvm/mmu.c | 17 +-
arch/arm64/mm/fault.c | 30 +-
arch/arm64/mm/fixmap.c | 36 +-
arch/arm64/mm/init.c | 2 +-
arch/arm64/mm/kasan_init.c | 159 +++++--
arch/arm64/mm/mmap.c | 4 +
arch/arm64/mm/mmu.c | 255 ++++++-----
arch/arm64/mm/pgd.c | 17 +-
arch/arm64/mm/proc.S | 122 +++++-
arch/arm64/mm/ptdump.c | 21 +-
arch/arm64/tools/cpucaps | 1 +
include/linux/mman.h | 15 +
mm/mmap.c | 3 +
53 files changed, 1948 insertions(+), 1116 deletions(-)
rename arch/arm64/kernel/{ => pi}/idreg-override.c (83%)
create mode 100644 arch/arm64/kernel/pi/map_kernel.c
create mode 100644 arch/arm64/kernel/pi/map_range.c
rename arch/arm64/kernel/{ => pi}/patch-scs.c (89%)
create mode 100644 arch/arm64/kernel/pi/pi.h
create mode 100644 arch/arm64/kernel/pi/relacheck.c
create mode 100644 arch/arm64/kernel/pi/relocate.cSignature · 7 lines
2.43.0.687.g38aa6559b0-goog _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel