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PCI: vmd: Enable PCI PM's L1 substates of remapped PCIe Root Port and NVMe

Jian-Hong Pan linux-pci lkml 11 versions – Applied

Status from this message: Applied to controller/vmd, thank you!

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Versions newest first · linked by author and title

  1. v12 Latest3 patches 10 repliesApplied
  2. v113 patches 1 replySuperseded
  3. v103 patches 2 repliesSuperseded
Earlier versions · 8
VersionPostedPatchesRepliesStatus
v93 patches6 repliesSuperseded
v84 patches17 repliesSuperseded
v74 patches0 repliesSuperseded
v63 patches6 repliesSuperseded
v54 patches11 repliesSuperseded
v43 patches7 repliesSuperseded
v33 patches4 repliesSuperseded
v21 patch9 repliesSuperseded

Patches in v12 Applied

#Subject and filesSizeRepliesApplied
1/3PCI: vmd: Set PCI devices to D0 before enable PCI PM's L1 substatesdrivers/pci/controller/vmd.c+9 -41 reply
2/3PCI/ASPM: Add notes about enabling PCI-PM L1SS to pci_enable_link_state(_locked)drivers/pci/pcie/aspm.c+6 -00 replies
3/3PCI/ASPM: Make pci_save_aspm_l1ss_state save both child and parent's L1SS configurationdrivers/pci/pcie/aspm.c+19 -19 replies

Reviews trailers per patch

All 3 patches have a Reviewed-by or Acked-by.

PatchKuppuswamy SathyanarayananBjorn HelgaasIlpo JärvinenDavid E. Box
1/3R-b
2/3R-b A-b
3/3R-b R-b R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 4 reviewers.

Read the v12 thread

Cover letter [PATCH v12 0/3] PCI: vmd: Enable PCI PM's L1 substates of remapped PCIe Root Port and NVMe

Notice the VMD remapped PCIe Root Port and NVMe have PCI PM L1 substates capability, but they are disabled originally.

Here is a failed example on ASUS B1400CEAE with enabled VMD:

10000:e0:06.0 PCI bridge [0604]: Intel Corporation 11th Gen Core Processor PCIe Controller [8086:9a09] (rev 01) (prog-if 00 [Normal decode])

    ...
    Capabilities: [200 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
                  PortCommonModeRestoreTime=45us PortTPowerOnTime=50us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
                   T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=0us

10000:e1:00.0 Non-Volatile memory controller [0108]: Sandisk Corp WD Blue SN550 NVMe SSD [15b7:5009] (rev 01) (prog-if 02 [NVM Express])

    ...
    Capabilities: [900 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+
                  PortCommonModeRestoreTime=32us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
                   T_CommonMode=0us LTR1.2_Threshold=101376ns
        L1SubCtl2: T_PwrOn=50us

According to "PCIe r6.0, sec 5.5.4", to config the link between the PCIe Root Port and the child device correctly:
* Ensure both devices are in D0 before enabling PCI-PM L1 PM Substates.
* Ensure L1.2 parameters: Common_Mode_Restore_Times, T_POWER_ON and LTR_L1.2_THRESHOLD are programmed properly on both devices before enable bits for L1.2.

Prepare this series to fix that.

Jian-Hong Pan (3):
PCI: vmd: Set PCI devices to D0 before enable PCI PM's L1 substates PCI/ASPM: Add notes about enabling PCI-PM L1SS to
pci_enable_link_state(_locked)
PCI/ASPM: Make pci_save_aspm_l1ss_state save both child and parent's
L1SS configuration

 drivers/pci/controller/vmd.c | 13 +++++++++----
 drivers/pci/pcie/aspm.c      | 26 +++++++++++++++++++++++++-
 2 files changed, 34 insertions(+), 5 deletions(-)
Signature · 1 line
2.46.2

Read the cover letter in its thread