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KVM: arm64: nv: Shadow stage-2 page table handling

Marc Zyngier kvm kvmarm linux-arm-kernel 3 versions – Applied

Status from this message: Applied to kvmarm/next, thanks!

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Versions newest first · linked by author and title

  1. v3 Latest16 patches 12 repliesApplied
  2. v216 patches 5 repliesSuperseded
  3. v116 patches 2 repliesSuperseded

Patches in v3 Applied

#Subject and filesSizeRepliesApplied
1/16KVM: arm64: nv: Support multiple nested Stage-2 mmu structuresarch/arm64/include/asm/kvm_host.h arch/arm64/include/asm/kvm_mmu.h arch/arm64/include/asm/kvm_nested.h +4 more+349 -210 replies
2/16KVM: arm64: nv: Implement nested Stage-2 page table walk logicarch/arm64/include/asm/esr.h arch/arm64/include/asm/kvm_nested.h arch/arm64/kvm/nested.c+278 -03 replies
3/16KVM: arm64: nv: Handle shadow stage 2 page faultsarch/arm64/include/asm/kvm_nested.h arch/arm64/kvm/mmu.c arch/arm64/kvm/nested.c+166 -92 replies
4/16KVM: arm64: nv: Unmap/flush shadow stage 2 page tablesarch/arm64/include/asm/kvm_mmu.h arch/arm64/include/asm/kvm_nested.h arch/arm64/kvm/mmu.c +1 more+70 -50 replies
5/16KVM: arm64: nv: Add Stage-1 EL2 invalidation primitivesarch/arm64/include/asm/kvm_asm.h arch/arm64/kvm/hyp/vhe/tlb.c+67 -00 replies
6/16KVM: arm64: nv: Handle EL2 Stage-1 TLB invalidationarch/arm64/include/asm/kvm_nested.h arch/arm64/include/asm/sysreg.h arch/arm64/kvm/hyp/vhe/switch.c+122 -10 replies
7/16KVM: arm64: nv: Handle TLB invalidation targeting L2 stage-1arch/arm64/include/asm/kvm_nested.h arch/arm64/kvm/nested.c arch/arm64/kvm/sys_regs.c+122 -00 replies
8/16KVM: arm64: nv: Handle TLBI VMALLS12E1{,IS} operationsarch/arm64/kvm/sys_regs.c+51 -00 replies
9/16KVM: arm64: nv: Handle TLBI ALLE1{,IS} operationsarch/arm64/kvm/sys_regs.c+25 -00 replies
10/16KVM: arm64: nv: Handle TLBI IPAS2E1{,IS} operationsarch/arm64/kvm/sys_regs.c+96 -00 replies
11/16KVM: arm64: nv: Handle FEAT_TTL hinted TLB operationsarch/arm64/include/asm/kvm_nested.h arch/arm64/kvm/nested.c arch/arm64/kvm/sys_regs.c+92 -230 replies
12/16KVM: arm64: nv: Tag shadow S2 entries with guest's leaf S2 levelarch/arm64/include/asm/kvm_nested.h arch/arm64/kvm/mmu.c+25 -20 replies
13/16KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like informationarch/arm64/kvm/nested.c+84 -10 replies
14/16KVM: arm64: nv: Add handling of outer-shareable TLBI operationsarch/arm64/kvm/hyp/vhe/tlb.c arch/arm64/kvm/nested.c arch/arm64/kvm/sys_regs.c+29 -10 replies
15/16KVM: arm64: nv: Add handling of range-based TLBI operationsarch/arm64/kvm/hyp/vhe/tlb.c arch/arm64/kvm/nested.c arch/arm64/kvm/sys_regs.c+108 -60 replies
16/16KVM: arm64: nv: Add handling of NXS-flavoured TLBI operationsarch/arm64/kvm/hyp/vhe/tlb.c arch/arm64/kvm/sys_regs.c+119 -00 replies

Reviews trailers per patch

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Read the v3 thread

Cover letter [PATCH v3 00/16] KVM: arm64: nv: Shadow stage-2 page table handling

Here's the thurd version of the shadow stage-2 handling for NV support on arm64.

* From v2 [2]

- Simplified the S2 walker by dropping a bunch of redundant fields from the walker info structure

- Added some more lockdep assertions (Oliver)

- Added more precise comments for the TTL-like annotations in the shadow S2 (Oliver)

* From v1 [1]

- Reworked the allocation of shadow S2 structures at init time to be slightly clearer

- Lots of small cleanups

- Rebased on v6.10-rc1

[1] https://lore.kernel.org/r/[email protected]

Christoffer Dall (2):
KVM: arm64: nv: Implement nested Stage-2 page table walk logic
KVM: arm64: nv: Unmap/flush shadow stage 2 page tables

Marc Zyngier (14):
KVM: arm64: nv: Support multiple nested Stage-2 mmu structures
KVM: arm64: nv: Handle shadow stage 2 page faults
KVM: arm64: nv: Add Stage-1 EL2 invalidation primitives
KVM: arm64: nv: Handle EL2 Stage-1 TLB invalidation
KVM: arm64: nv: Handle TLB invalidation targeting L2 stage-1
KVM: arm64: nv: Handle TLBI VMALLS12E1{,IS} operations
KVM: arm64: nv: Handle TLBI ALLE1{,IS} operations
KVM: arm64: nv: Handle TLBI IPAS2E1{,IS} operations
KVM: arm64: nv: Handle FEAT_TTL hinted TLB operations
KVM: arm64: nv: Tag shadow S2 entries with guest's leaf S2 level
KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like
information
KVM: arm64: nv: Add handling of outer-shareable TLBI operations
KVM: arm64: nv: Add handling of range-based TLBI operations
KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations

 arch/arm64/include/asm/esr.h        |   1 +
 arch/arm64/include/asm/kvm_asm.h    |   2 +
 arch/arm64/include/asm/kvm_host.h   |  36 ++
 arch/arm64/include/asm/kvm_mmu.h    |  26 +
 arch/arm64/include/asm/kvm_nested.h | 127 +++++
 arch/arm64/include/asm/sysreg.h     |  17 +
 arch/arm64/kvm/arm.c                |  11 +
 arch/arm64/kvm/hyp/vhe/switch.c     |  51 +-
 arch/arm64/kvm/hyp/vhe/tlb.c        | 147 ++++++
 arch/arm64/kvm/mmu.c                | 213 ++++++--
 arch/arm64/kvm/nested.c             | 781 +++++++++++++++++++++++++++-
 arch/arm64/kvm/reset.c              |   6 +
 arch/arm64/kvm/sys_regs.c           | 398 ++++++++++++++
 13 files changed, 1775 insertions(+), 41 deletions(-)
Signature · 1 line
2.39.2