riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes
Status from this message: Applied to riscv-dt-for-next, thanks!
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v3 Latest4 patches 5 repliesApplied
- v25 patches 26 repliesSuperseded
- v1 RFC3 patches 5 repliesSuperseded
Changes in v3 from the cover letter
- 1/5 -> 1/4: Do not replace assigned CPU core or PLL0 clock when adding new assignments. Adjust patch name and commit message accordingly.
- 2/5 -> 2/4: Detail reason for qspi setting changes in commit message
- 3/5 -> Drop uart0 clock-frequency patch
- 4/5 -> 3/4: Add reviewed by tag (no change)
- 5/5 -> 4/4: Follow dts coding style sort order. Add bootph-pre-ram hint for mmc interfaces
Patches in v3 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/4 | riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrgarch/ | +10 | 1 reply | |
| 2/4 | riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHzarch/ | +2 | 1 reply | |
| 3/4 | riscv: dts: starfive: jh7110-common: add eeprom node to i2c5arch/ | +6 | 0 replies | |
| 4/4 | riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loaderarch/ | +9 | 1 reply |
Reviews trailers per patch
All 4 patches have a Reviewed-by or Acked-by.
| Patch | Hal Feng | Emil Renner Berthing |
|---|---|---|
| 1/4 | R-b | |
| 2/4 | R-b | A-b |
| 3/4 | R-b | R-b |
| 4/4 | A-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes
U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts with StarFive VisionFive2 board target (and related JH7110 common boards). Sync the minimum changes from jh7110-common.dtsi needed for boot so these can be dropped from U-Boot.
Changes since v2:
- 1/5 -> 1/4: Do not replace assigned CPU core or PLL0 clock when adding new assignments. Adjust patch name and commit message accordingly.
- 2/5 -> 2/4: Detail reason for qspi setting changes in commit message
- 3/5 -> Drop uart0 clock-frequency patch
- 4/5 -> 3/4: Add reviewed by tag (no change)
- 5/5 -> 4/4: Follow dts coding style sort order. Add bootph-pre-ram hint for mmc interfaces
Note: mmc boot source modes of JH7110 loader on mask ROM are deprecated as of StarFive JH7110 User Guide 1.2 revision. The loader expects data within range of LBA 0 and LBA 1 in conflict with GUID Partition Table.
SD Card and eMMC boot media are prepared as follows:
# GPT partition SD Card or eMMC as
# 1: Secondary Program Loader @ 0x200000
# 2: Main payload area for use by SPL
# 3: EFI System Partition
sgdisk --clear \
--new=1:2M:+2M --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \
--new=2:4M:+4M --typecode=2:5B193300-FC78-40CD-8002-E86C45580B47 \
--new=3:8M:+100M --typecode=3:EF00 /dev/sdX
# Write offset value in bytes of loader 'backup section' SPL as part1 @ 2M python3 <<-EOF
with open("/dev/sdX", "r+b") as f:
f.seek(0x0004)
f.write((0x200000).to_bytes(4, "little"))
EOF
# Write invalid CRC to trigger 'Main section boot fail,use backup section' python3 <<-EOF
with open("/dev/sdX", "r+b") as f:
f.seek(0x0290)
f.write((0x5A5A5A5A).to_bytes(4, "little"))
EOF
E Shattow (4):
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to
syscrg
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2
cycles max 100MHz
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by
boot loader
.../boot/dts/starfive/jh7110-common.dtsi | 31 ++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-)
base-commit: ebd297a2affadb6f6f4d2e5d975c1eda18ac762d
Signature · 7 lines
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