drm/i915/tc: Fix enabled/disconnected DP-alt sink handling
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- v1 Latest19 patches 31 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/19 | drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sinkdrivers/ | +10 | 9 replies | |
| 2/19 | drm/i915/icl+/tc: Cache the max lane count valuedrivers/ | +42 | 2 replies | |
| 3/19 | drm/i915/lnl+/tc: Fix max lane count HW readoutdrivers/ | +9 | 2 replies | |
| 4/19 | drm/i915/lnl+/tc: Use the cached max lane count valuedrivers/ | +5 | 1 reply | |
| 5/19 | drm/i915/icl+/tc: Convert AUX powered WARN to a debug messagedrivers/ | +3 | 1 reply | |
| 6/19 | drm/i915/tc: Use the cached max lane count valuedrivers/ | +0 | 1 reply | |
| 7/19 | drm/i915/tc: Move getting the power domain before reading DFLEX registersdrivers/ | +8 | 1 reply | |
| 8/19 | drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUSdrivers/ | +4 | 1 reply | |
| 9/19 | drm/i915/tc: Add an enum for the TypeC pin assignmentdrivers/ drivers/ drivers/ | +78 | 1 reply | |
| 10/19 | drm/i915/tc: Pass pin assignment value around using the pin assignment enumdrivers/ drivers/ drivers/ | +20 | 1 reply | |
| 11/19 | drm/i915/tc: Handle pin assignment NONE on all platformsdrivers/ | +2 | 1 reply | |
| 12/19 | drm/i915/tc: Validate the pin assignment on all platformsdrivers/ | +23 | 1 reply | |
| 13/19 | drm/i915/tc: Unify the way to get the pin assignment on all platformsdrivers/ | +27 | 1 reply | |
| 14/19 | drm/i915/tc: Unify the way to get the max lane count value on MTL+drivers/ | +0 | 1 reply | |
| 15/19 | drm/i915/tc: Handle non-TC encoders when getting the pin assignmentdrivers/ | +3 | 1 reply | |
| 16/19 | drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpersdrivers/ | +7 | 1 reply | |
| 17/19 | dmc/i915/tc: Report pin assignment NONE in TBT-alt modedrivers/ | +3 | 1 reply | |
| 18/19 | drm/i915/tc: Cache the pin assignment valuedrivers/ | +3 | 1 reply | |
| 19/19 | drm/i915/tc: Debug print the pin assignment and max lane countdrivers/ | +17 | 1 reply |
Reviews trailers per patch
All 19 patches have a Reviewed-by or Acked-by.
| Patch | Khaled Almahallawy | Mika Kahola | Luca Coelho |
|---|---|---|---|
| Series | T-b | ||
| 1/19 | T-b | R-b | R-b |
| 2/19 | T-b T-b | R-b | |
| 3/19 | T-b T-b | R-b | |
| 4/19 | T-b | R-b | |
| 5/19 | T-b | R-b | |
| 6/19 | R-b | ||
| 7/19 | R-b | ||
| 8/19 | R-b | ||
| 9/19 | R-b | ||
| 10/19 | R-b | ||
| 11/19 | R-b | ||
| 12/19 | R-b | ||
| 13/19 | R-b | ||
| 14/19 | R-b | ||
| 15/19 | R-b | ||
| 16/19 | R-b | ||
| 17/19 | R-b | ||
| 18/19 | R-b | ||
| 19/19 | R-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.
Cover letter [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling
This patchset fixes an issue on LNL+, where the TypeC PHY's mode/state is detected incorrectly during HW readout for a DP-alt sink that got enabled by BIOS/GOP, but later the sink got disconnected by the user before the driver got loaded.
The issue in the driver is due to overlooking a change on LNL+ in the way the PHY ready flag and pin assignment is set/cleared in the PHY registers by the HW/FW wrt. how this works on all the earlier (ICL-MTL) TypeC platforms.
The first 5 patches fix the issue, the rest refactor the PHY's max lane count and pin assignment query functions, sanitizing the code, removing duplications and validating the register values read out from the HW.
Imre Deak (19):
drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink drm/i915/icl+/tc: Cache the max lane count value drm/i915/lnl+/tc: Fix max lane count HW readout drm/i915/lnl+/tc: Use the cached max lane count value drm/i915/icl+/tc: Convert AUX powered WARN to a debug message drm/i915/tc: Use the cached max lane count value drm/i915/tc: Move getting the power domain before reading DFLEX
registers
drm/i915/tc: Move asserting the power state after reading
TCSS_DDI_STATUS
drm/i915/tc: Add an enum for the TypeC pin assignment drm/i915/tc: Pass pin assignment value around using the pin assignment
enum
drm/i915/tc: Handle pin assignment NONE on all platforms drm/i915/tc: Validate the pin assignment on all platforms drm/i915/tc: Unify the way to get the pin assignment on all platforms drm/i915/tc: Unify the way to get the max lane count value on MTL+ drm/i915/tc: Handle non-TC encoders when getting the pin assignment drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers dmc/i915/tc: Report pin assignment NONE in TBT-alt mode drm/i915/tc: Cache the pin assignment value
drm/i915/tc: Debug print the pin assignment and max lane count
drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- .../gpu/drm/i915/display/intel_display_regs.h | 2 + drivers/gpu/drm/i915/display/intel_tc.c | 217 ++++++++++++------ drivers/gpu/drm/i915/display/intel_tc.h | 72 +++++- 4 files changed, 225 insertions(+), 85 deletions(-)
Signature · 1 line
2.49.1