Add cache information to Amlogic SoC
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Changes from the cover letter
v3: Drop the commit message as per Krzysztof feedback.
v2: Modified the commit message and added cache information few more SoC.
v1: https://lists.infradead.org/pipermail/linux-arm-kernel/2024-February/901497.html
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Cover letter [PATCH v3 00/11] Add cache information to Amlogic SoC
Most publicly available Amlogic datasheets mention that the CPU employs a architecture, quad-core ARM Cortex-A53 and ARM Cortex A55 and Cortex-A73 and Cortex-A53 cluster, sharing a unified L2 cache to enhance overall system performance.
However, these documents typically omit details regarding the sizes of the L1 data cache, L1 instruction cache, and L2 cache.
The patches in question align with the cache specifications provided by ARM TRM for the respective CPU cores.
ARM Cortex-A53
L1: 32KB instruction + 32KB data cache
L2: Unified 512KB cache
L1 cache details, L2 cache details
[1] https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System/About-the-L1-memory-system?lang=en
[2] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
ARM Cortex-A55
Cache sizes are implementation-dependent; refer to ARM documentation for configuration options.
ARM Cortex-A73 (as used in Amlogic S922X and T7)
L1: Configurable, typically 64KB instruction + 64KB data
L2: Unified cache, configurable up to 1MB or more L2 cache details,
4× Cortex-A73 cores (up to 1.8GHz) with 1MB shared L2 cache 2× Cortex-A53 cores with 256KB shared L2 cache
[4] https://developer.arm.com/documentation/100048/0100/level-1-memory-system/about-the-l1-memory-system?lang=enL2
[5] https://developer.arm.com/documentation/100048/0100/level-2-memory-system/about-the-l2-memory-system?lang=en
[6] https://androidpctv.com/comparative-amlogic-s922x/
Changes:
v3: Drop the commit message as per Krzysztof feedback.
v2: Modified the commit message and added cache information few more SoC.
v1: https://lists.infradead.org/pipermail/linux-arm-kernel/2024-February/901497.html
Thanks
-Anand
Anand Moon (11):
arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL
SoC
arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 37 +++++++++++ arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 23 +++++++ arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 36 ++++++++++ arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 21 ++++++ arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 ++++++++ arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 +++++++++++++++-- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 27 ++++++++ arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 24 +++++++ arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 27 ++++++++ 11 files changed, 366 insertions(+), 7 deletions(-)
base-commit: d69eb204c255c35abd9e8cb621484e8074c75eaa
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2.50.1