RFC alternate 4-level page tables patches
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- v1 RFC Latest10 patches 66 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/10 | alternate 4-level page tables patchesinclude/ | +59 | 0 replies | |
| 2/10 | alternate 4-level page tables patchesinclude/ include/ include/ +4 more | +31 | 0 replies | |
| 3/10 | alternate 4-level page tables patchesmm/ | +152 | 0 replies | |
| 4/10 | alternate 4-level page tables patchesinclude/ mm/ mm/ | +58 | 25 replies | |
| 5/10 | alternate 4-level page tables patchesinclude/ include/ include/ | +91 | 0 replies | |
| 6/10 | alternate 4-level page tables patchesdrivers/ fs/ include/ +10 more | +644 | 0 replies | |
| 7/10 | alternate 4-level page tables patchesarch/ arch/ arch/ +8 more | +81 | 0 replies | |
| 8/10 | alternate 4-level page tables patchesarch/ arch/ arch/ +3 more | +50 | 0 replies | |
| 9/10 | alternate 4-level page tables patchesDocumentation/ arch/ arch/ +15 more | +314 | 0 replies | |
| 10/10 | alternate 4-level page tables patchesmm/ mm/ mm/ +1 more | +15 | 14 replies |
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Cover letter [RFC][PATCH 0/10] alternate 4-level page tables patches
Hi,
Apologies for not making progress on this done sooner, but better late than never.
First off - don't let all the signed-off-by: things fool you, I'm only intending this for comments, not merging. I just spent a bit of time getting the descriptions in better shape.
Second - much of it is Andi's code (especially 4 level core, and x86-64 stuff). If any attributions aren't quite accurate at this stage, don't worry too much!
Anyway, although we have a working 4-level page tables implementation, I am keeping with this because my personal taste preference. Not that it is anything against Andi's taste or technical implementation... but I wouldn't like progress to be held up on account of me, so I wouldn't be too upset to forget about this until 2.7 (or for ever)... /end disclaimer
Well, the patches follow. Tested lightly on i386 32 and 36 bits, ia64, and x86-64 with full 4 levels.
Comments?
Nick
A bit of an aside: I was hoping to have a page table folding implementation that is basically transparent to architectures. That is, a 3-level arch could just include some generic header to fold the 4th level, and call it a day (without any other mods to arch/?/* or include/asm-?/*).
The reality is, this isn't going to happen with our current semantics. It probably isn't a really big deal though, because I don't expect we'd have to support a 5 level implementation any time soon. But it is something I'd like to explore further.
I'll illustrate with an example: in the current setup, if the pmd is folded into the pgd, pgd_present is always true, and pmd_present is what actually examines the entry in the pgd. Now clearly, the architecture has to implement pmd_present, which is pgd_present in a 2-level setup.
I would like to change that so pgd_present really does check the actual pgd entry, and pmd_present is unconditionally true. IMO this would work better and be less confusing than the current setup... but that's getting off topic...
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