svm: implement new DecodeAssist feature
Status from this message: Applied as c/2 23236. Fixed to not handle the INVLPGA exit code.
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Patches in v1 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/5 | vmx/hvm: move mov-cr handling functions to generic HVM codexen/ xen/ xen/ +2 more | +170 | 1 reply | |
| 2/5 | svm: add bit definitions for SVM DecodeAssistxen/ xen/ xen/ | +5 | 0 replies | |
| 3/5 | svm: implement instruction fetch part of DecodeAssistxen/ xen/ xen/ | +35 | 2 replies | |
| 4/5 | svm: implement CR access part of DecodeAssistxen/ | +29 | 0 replies | |
| 5/5 | svm: implement INVLPG part of DecodeAssistxen/ | +4 | 1 reply |
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Cover letter [PATCH 0/5] svm: implement new DecodeAssist feature
Hi,
newer AMD SVM implementations (starting with Bulldozer) have some additions to SVM called DecodeAssist. These bits improve and simplify the handling of some intercepts, now more information is provided in the VMCB already and saves us from decoding this information "manually". These new features are described in recent editions of the APM Vol.2 manual, chapter 15.33.
The first patch moves some code from VMX into HVM to be later used by SVM. The second patch adds the newly defined bits to VMCB and CPUID. Patch 3 to 5 implement three parts of the feature set, more details in the specific emails.
Please comment.
All patches:
Regards,
Andre.
Signature · 2 lines
Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany