RFC dt: device tree bindings and data for EMIF and DDR
Get series with b4
b4 am [email protected]Versions newest first
- v2 RFC Latest0 of 3 patches 0 repliesNew
Patches in v2 No applies recorded yet
None of the 3 patches the cover letter announces are in this archive.
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v2 yet.
Cover letter [RFC v2 PATCH 0/3] dt: device tree bindings and data for EMIF and DDR
Quoted 10 lines · Aneesh V
This is an RFC to add new device tree bindings for DDR memories and EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently, we have added properties for only DDR3 and LPDDR2 memories. However, the binding can be easily extended to describe other types such as DDR2 in the future.
The second patch provides the bindings for the EMIF controller.
Quoted 8 lines
The final patch provides DT data for EMIF controller instances in OMAP4 and LPDDR2 memories attached to them on various boards.
Thanks to Rajendra for answering my numerous queries on device tree.
This is a re-post of the RFC that was posted to devicetree-discuss ml, now sent to a larger audience and looping out an internal list. Please ignore the previous version.
There's already a standard way (i.e. JEDEC standard) to define DDR chip configuration that's called SPD. Why invent something new? While this is normally an i2c eeprom on a DIMM, there's no reason you couldn't get it from somewhere else including perhaps the DT. There's already code in u-boot that can parse SPD data.
In general, is it really feasible to parse the DTB before DDR is initialized?
Rob