ARM: OMAP2+: PM: implement a caching mechanism on the power domains state registers
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| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 2/5 | ARM: OMAP2+: PM: use the power domains registers cache for the power states | +0 | 2 replies | |
| 3/5 | ARM: OMAP2+: PM: use the power domains registers cache for the logic and mem states | +0 | 0 replies |
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Cover letter [PATCH 0/5] ARM: OMAP2+: PM: implement a caching mechanism on the power domains state registers
Hi Jean,
Quoted 18 lines · jean.pihet at newoldbits.com
From: Jean Pihet <[email protected]>
The OMAP3 PRCM registers accesses are known to be slow, with a PRCM register read taking up to 12-14us depending on the OPP.
This patch adds a caching mechanism on the power domains state registers. When the cache is cold or has been invalidated a register access is performed, otherwise the register value is retrieved from the registers cache.
The API is made of read and write functions for fields in the cache, as well as an invalidate and helper functions to invalidate parts of the cache contents (i.e. previous, current power states and all fields in the cache). The power domain code is converted to use the API to read and write the previous, current and next states for the power domains states, logical and memory states.
The PM debug code also uses the caching API instead of the internalpwrdm->statevariable.
Quoted 2 lines
Using the caching mechanism optimizes the performance of the system in the transitions to and from the low power states.
Looks interesting!
A couple high level questions for you ...
1. Do you intend to cache registers that are updated by hardware?
2. If yes to 1, should there be some "cache debug mode" we can enable to test the cache and registers are in sync for testing?
Cheers
Jon