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tegra: Add display driver and LCD support for Seaboard

Stephen Warren linux-devicetree u-boot 6 versions – New

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  1. v4 Latest posting 5/50 of 16 patches 0 repliesNew
  2. v4 posting 4/51 of 16 patches 0 repliesSuperseded
  3. v4 posting 3/50 of 16 patches 0 repliesSuperseded
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v4 posting 2/50 of 16 patches0 repliesSuperseded
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Patches in v4 posting 5/5 No applies recorded yet

None of the 16 patches the cover letter announces are in this archive.

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Cover letter [U-Boot] [PATCH v4 0/16] tegra: Add display driver and LCD support for Seaboard
Quoted 55 lines · Simon Glass

Hi Stephen,

Quoted 52 lines · Stephen Warren
Quoted 19 lines · Simon Glass

Hi Stephen,

Quoted 16 lines · Stephen Warren
Quoted 4 lines · Stephen Warren
Quoted 3 lines · Simon Glass

This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.

...

Quoted 7 lines

2) The display works fine for cold boot, or hitting the physical reset button, but when I execute "reset" at the U-Boot prompt, or "reboot" within Linux, the display is messed up; it looks like the LCD isn't able to sync to the timings sent by the display controller or something similar.

Since this is slightly a corner case, it may be OK to fix it later (but not much later; reboot is very useful to me.)

A couple more points:

Quoted 7 lines
Quoted 5 lines

BTW, I tried the same tests on Springbank which is basically Seaboard with a slightly different PCB layout, and didn't see this issue. That leads me to suspect some timing issue interacting with the panel, which I believe is different albeit theoretically compatible resolution/scan-timing wise.

OK. I wonder the panel does not get reset properly on Seaboard?

I looked at the panel spec for the panels on the two boards. Both of them specify that when vdd_pnl is dropped to zero, you must wait at least 400mS before raising it again. Evidently the Seaboard panel actually cares about this, yet the Springbank panel seems to be more flexible than the specification. So, modifying drivers/video/tegra.c:handle_stage() case STAGE_START to:

    if (fdt_gpio_isvalid(&config.panel_vdd)) {
        udelay(400000);
        gpio_direction_output(config.panel_vdd.gpio, 1);
    }

... appears to solve the problem; I can run "reset" in U-Boot many many times without any issue after that change.

I guess this means that the nvidia,panel-timings DT property needs a pre-delay entry for STAGE_START, or something like that?

Also, I wondered if we shouldn't explicitly do:

    gpio_direction_output(config.panel_vdd.gpio, 0);
    udelay(400000);
    gpio_direction_output(config.panel_vdd.gpio, 1);
Quoted 5 lines
Quoted 3 lines

... although that doesn't make a difference; the particular GPIO used on Seaboard appears to default to 0. I'm not sure that all GPIOs are guaranteed to though.

So reset is causing the line to go low?

I would imagine so.

Quoted 3 lines

OK, there's probably nothing
we can do here except wait for 400ms. Is there any way to detect this condition? Adding 400ms is quite a big jump in boot time.

I think the PMIC has a "power-on/reset reason" register. However, I don't know exactly how long the minimum time between powering off and immediately powering on is; it's plausible it isn't safe to skip some waiting even in that case.