RFC SATA support for OMAP5 uevm

Roger,

Quoted 118 lines

-----Original Message-----
From: Quadros, Roger
Sent: Monday, November 11, 2013 5:16 AM
To: V, Aneesh
Cc: Enric Balletbo Serra; u-boot at lists.denx.de; Rini, Tom; Krishnamoorthy, Balaji T; rob.herring at calxeda.com
Subject: Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm

Aneesh,

Quoted 74 lines · Aneesh

Hi Roger,

Quoted 72 lines

-----Original Message-----
From: Quadros, Roger
Sent: Thursday, November 07, 2013 2:45 AM
To: Enric Balletbo Serra
Cc: u-boot at lists.denx.de; Rini, Tom; Krishnamoorthy, Balaji T; rob.herring at calxeda.com; V, Aneesh
Subject: Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm

+Aneesh.

Hi Enric,

Quoted 26 lines · Enric Balletbo Serra

Hi Roger,

Thanks for the patches!

2013/11/6 Roger Quadros <[email protected]>:

Quoted 21 lines

Hi,

This series adds SATA support for OMAP5 uevm board.

This is an RFC patchset for review only. Patches are based on v2013.10.

cheers,
-roger

---
Roger Quadros (5):
ahci: Error out with message on malloc() failure
ARM: OMAP5: Add Pipe3 PHY driver
ARM: OMAP5: Add PRCM and Control information for SATA
ARM: OMAP5: Add SATA platform glue
ARM: omap5_uevm: Add SATA support

 arch/arm/cpu/armv7/omap-common/Makefile    |   7 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233

+++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-

common/pipe3-phy.h | 36 +++++

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 arch/arm/cpu/armv7/omap-common/sata.c      |  78 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   5 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   3 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  16 +-
 include/configs/omap5_uevm.h               |  10 ++
 12 files changed, 447 insertions(+), 2 deletions(-)  create mode
100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h

Quoted 7 lines

--
1.8.3.2

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I applied your patches and worked perfectly, however I've two small issues.

The first issue is that I see the following error:

scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned -
0xfee48818

Quoted 7 lines

Quoted 2 lines

I'm seeing this too. Not sure how to fix it.
Aneesh, any pointers?

The issue is that the dcache invalidation is requested for a buffer that is not aligned to cache-line boundary. The cpu instructions for cache invalidation operate on cache lines, so a cache line can not be invalidated partially. So in this case the invalidation function will refuse to

invalidate the first and last cache lines.

Quoted 7 lines

The solution is to align your DMA buffer correctly. Take a look at :

ALLOC_CACHE_ALIGN_BUFFER() and DEFINE_CACHE_ALIGN_BUFFER() in include/common.h

Also, doc/README.arm-caches has instructions for handling cached buffers

for DMA.

Thanks for this tip, it helped.

One more thing. While I was looking at arch/arm/cpu/armv7/cache_v7.c I failed to understand how you convert the cache line size from words to byte.

e.g.

Quoted 9 lines

static void v7_maint_dcache_level_setway(u32 level, u32 operation) {
        u32 ccsidr;
        u32 num_sets, num_ways, log2_line_len, log2_num_ways;
        u32 way_shift;

        set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);

        ccsidr = get_ccsidr();

Quoted 7 lines

Quoted 4 lines

        log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
                                CCSIDR_LINE_SIZE_OFFSET) + 2;
        /* Converting from words to bytes */
        log2_line_len += 2;

Shouldn't this be

	log2_line_len += 1;

I don?t remember the details of that calculation. But assuming 32-bit word and this variable representing the log2 of the line length it should be +=2 right? Let's say 32 bytes, which is the cache-line size of A15:

32 bytes = 8 words = 2^3 words
32 bytes = 2^5 bytes