clk: socfpga: add divider registers to the main pll outputs
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b4 am [email protected]Versions newest first
- v1 Latest2 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/2 | clk: socfpga: add divider registers to the main pll outputs | +0 | 1 reply | |
| 1/2 | clk: socfpga: add divider registers to the main pll outputs | +0 | 1 reply |
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