Add LS1021A-QDS/TWR Non-secure and HYP support.
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- v1 Latest4 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/4 | ARM: fix the ARCH Timer frequency setting. | +0 | 1 reply | |
| 1/4 | ARM: fix the ARCH Timer frequency setting. | +0 | 0 replies | |
| 3/4 | ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 | +0 | 1 reply | |
| 3/4 | ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 | +0 | 1 reply | |
| 4/4 | ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region | +0 | 1 reply |
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Cover letter [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
Quoted 7 lines · Xiubo Li
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe
But we have HYP enabled. In this case why are the series dependent on this patch?
Quoted 19 lines
timers that are not synchronized, effectively seeing time going backward...
Patch work:
http://patchwork.ozlabs.org/patch/343084/Xiubo Li (4):
ARM: fix the ARCH Timer frequency setting.
ARM: add the pen address byte reverting support.
ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
ARM: LS1021A: to allow non-secure R/W access for all devices' mapped
region
Quoted 8 lines
arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++-- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-)
Diana