Skip to content

spi: cadence_qspi: sram depth from DT & fix for FIFO width

Stefan Roese u-boot 1 version New

Get series with b4
b4 am [email protected]

Versions newest first

  1. v1 Latest0 of 3 patches 0 repliesNew

Patches in v1 No applies recorded yet

None of the 3 patches the cover letter announces are in this archive.

Reviews trailers per patch

No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.

Read the v1 thread

Cover letter [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 10 lines · Vikas MANOCHA
Quoted 10 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot at lists.denx.de;
grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 7 lines
Quoted 5 lines · Vikas MANOCHA
Quoted 1 line

Any comments on the patchset.

I'll test them next week on a SoCFPGA based board and will comment then again.

Can you please test this patchset also.

Okay. I've now tested this 3 patch series as well on top of mainline. And SPI NOR seems to work just fine with this one applied. Not errors and the write/read/compare test also works okay.

HTP.

Thanks,
Stefan

Read the cover letter in its thread