dcache support for Raspberry Pi 1
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- v1 Latest5 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/5 | arm1176/cpu: Match cache_flush to arm1136 | +0 | 1 reply | |
| 2/5 | arm1176/cpu: Add icache and dcache support | +0 | 1 reply | |
| 2/5 | arm1176/cpu: Add icache and dcache support | +0 | 0 replies | |
| 3/5 | arm1176/cpu: Align cache flushing addresses to cacheline size | +0 | 0 replies | |
| 4/5 | arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox | +0 | 0 replies | |
| 5/5 | arm/rpi: Enable dcache | +0 | 1 reply | |
| 5/5 | arm/rpi: Enable dcache | +0 | 0 replies |
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Cover letter [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1
Quoted 5 lines · Alexander Stein
This patchset enables dcache support for Raspberry Pi 1.
First the cache support code was made similar to existing arm1136 code. The invalidate and flush functions were inprovoed to accept also non-cacheline aligned addresses. This reduces the cacheline size knowledge from generic code.
As mentioned in some other responses, client code must be aware of the cacheline size, so the cache management code shouldn't try to handle misaligned requests, but should error out.
BTW, ALLOC_ALIGN_BUFFER() is probably what you need to fix any misbehaved client code.