Revert arm64 cache geometry
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Cover letter [PATCH 0/3] Revert arm64 cache geometry
Quoted 13 lines · Catalin Marinas
Quoted 12 lines · Sudeep Holla
Quoted 6 lines · Catalin Marinas
BTW, it looks like I don't get any cache information on Juno with 4.3-rc7, it says "Unable to detect cache hierarchy from DT for CPU 0". I thought the point of the patch you are trying to revert was to parse this information from the hardware registers. Sudeep, any idea?
Yes you need to have updated DT from the mainline. Since the architecture doesn't provide any way of detecting the cpus sharing particular cache, we get that information from DT.
Quoted 8 lines
Quoted 3 lines
If DT lacks that info we don't expose any information. It would be wrong to say that a shared cache is shared by all the cpus in the system. DT check was added explicitly to avoid that.
OK, thanks for the information. The good thing is that use space should already be able to cope with cache information not present in sysfs.
True.
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So, rather than reverting this feature, for the Denver case we have the option of either providing full cache topology information in DT or providing a DT flag which states whether hardware cache ID information is relevant.
Yes at-least few L2 cache controllers where either hardware can't provide that information or provides incorrect one, already use/override values from DT.
We can probably patch core cacheinfo itself as PPC also completely depends on DT(though not yet migrated to use generic cacheinfo). In that way we can avoid calling arch code if all the information is found in DT.
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What about ACPI? Are there any provisions for specifying such information?
Not yet.
Signature · 2 lines
Regards, Sudeep