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Enable high speed and heavy load for DDR4 for LSCH3

York Sun u-boot 1 version New

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  1. v1 Latest0 of 7 patches 0 repliesNew

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Cover letter [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3
Quoted 10 lines · Joakim Tjernlund
Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

Quoted 8 lines
 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

Quoted 10 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

York

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