RFC arm64: Scalable Vector Extension core support
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Cover letter [RFC PATCH 00/29] arm64: Scalable Vector Extension core support
Quoted 12 lines · Florian Weimer
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By the way, how is this implemented? Some of them overlap existing callee-saved registers.
Basically, all the *new* state is caller-save.
The Neon/FPSIMD regs V8-V15 are callee-save, so in the SVE view Zn[bits 127:0] is callee-save for all n = 8..15.
Are the extension parts of registers v8 to v15 used for argument passing?
If not, we should be able to use the existing dynamic linker trampoline.
if sve arguments are passed to a function then it has special call abi (which is probably not yet documented), this call abi requires that such a call does not go through plt to avoid requiring sve aware libc.
same for tls access: the top part of sve regs have to be saved by the caller before accessing tls so the tlsdesc entry does not have to save them.
so current trampolines should be fine.