mx5/6: Define default SoC input clock frequencies
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b4 am [email protected]Versions newest first · linked by author and title
- v2 Latest posting 2/214 patches 0 repliesNew
- v2 posting 1/22 patches 0 repliesSuperseded
- v11 patch 0 repliesSuperseded
Patches in v2 posting 2/2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/14 | mx5/6: Define default SoC input clock frequenciesarch/ arch/ arch/ +13 more | +64 | 2 replies | |
| 1/14 | mx5/6: Define default SoC input clock frequencies | +0 | 1 reply | |
| 2/14 | mx5 clocks: Cleanuparch/ arch/ | +184 | 1 reply | |
| 3/14 | mx5: Use explicit clock gate namesarch/ arch/ drivers/ | +284 | 1 reply | |
| 4/14 | mx5: Fix clock gate valuesarch/ arch/ | +18 | 0 replies | |
| 5/14 | mx51: Fix USB PHY clocksarch/ arch/ drivers/ | +24 | 4 replies | |
| 5/14 | mx51: Fix USB PHY clocks | +0 | 1 reply | |
| 5/14 | mx51: Fix USB PHY clocks | +0 | 1 reply | |
| 6/14 | mx5 clocks: Add and use CCSR definitionsarch/ arch/ | +46 | 0 replies | |
| 7/14 | mx5 clocks: Fix get_lp_apm()arch/ arch/ | +38 | 0 replies | |
| 8/14 | mx5 clocks: Fix get_periph_clk()arch/ | +22 | 0 replies | |
| 9/14 | mx5 clocks: Fix get_ipg_per_clk()arch/ | +7 | 1 reply | |
| 9/14 | mx5 clocks: Fix get_ipg_per_clk() | +0 | 1 reply | |
| 9/14 | mx5 clocks: Fix get_ipg_per_clk() | +0 | 1 reply | |
| 10/14 | mx5 clocks: Fix get_uart_clk()arch/ | +24 | 0 replies | |
| 11/14 | mx5 clocks: Simplify imx_get_cspiclk()arch/ | +3 | 0 replies | |
| 12/14 | mx5 clocks: Fix MXC_FEC_CLKarch/ | +2 | 0 replies | |
| 13/14 | mx51: Fix I2C clock ID checkarch/ | +5 | 0 replies | |
| 14/14 | mx5/6 clocks: Fix SDHC clocksarch/ arch/ arch/ | +67 | 0 replies |
Reviews trailers per patch
7 of 19 patches have a Reviewed-by or Acked-by.
| Patch | Marek Vasut | Stefano Babic | Igor Grinberg |
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| 1/14 | A-b T-b | ||
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| 2/14 | A-b | ||
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| 5/14 | R-b | A-b | |
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Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.