L2-cache synchronization for ppc44x

Yuri Tikhonov linuxppc-dev 1 version Nov 6, 2007 In review

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v1 Latest Nov 6, 20072 patches 13 repliesIn review

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#	Subject and files	Size	Replies	Applied
1/2	invalidate_l2cache_range() implementation for ppc44x`arch/powerpc/lib/dma-noncoherent.c` `arch/ppc/kernel/misc.S` `include/asm-powerpc/cache.h` +2 more	+39 -2	2 replies
2/2	enable L2-cache for ALPR, Katmai, Ocotea, and Taishan`arch/ppc/platforms/4xx/Kconfig` `arch/ppc/platforms/4xx/alpr.c` `arch/ppc/platforms/4xx/katmai.c` +2 more	+31 -0	5 replies

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Cover letter [PATCH 0/2] [PPC 4xx] L2-cache synchronization for ppc44x

Hello all,

Here is a patch-set for support L2-cache synchronization routines for
the ppc44x processors family. I know that the "ppc" branch is for bug-fixing only, thus the patch-set is just FYI [though enabled but non-coherent L2-cache may appear as a bug for someone who uses one of the boards listed below :)].

[PATCH 1/2] [PPC 4xx] invalidate_l2cache_range() implementation for ppc44x; [PATCH 2/2] [PPC 44x] enable L2-cache for the following ppc44x-based boards: ALPR, Katmai, Ocotea, and Taishan.

Regards, Yuri

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Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

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