Add System Error Interrupt support to Armada SoCs
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- v6 Latest2 of 14 patches 0 repliesNew
2 of 14 patches are in this archive. The cover letter announces 14.
Patches in v6 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 12/14 | arm64: dts: marvell: add AP806 SEI subnode | +0 | 0 replies | |
| 13/14 | arm64: dts: marvell: use new bindings for CP110 interrupts | +0 | 0 replies |
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No Reviewed-by, Acked-by or Tested-by trailers for v6 yet.
Cover letter [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs
Hi Marc,
Quoted 15 lines · Marc Zyngier
Quoted 12 lines · Miquel Raynal
The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired inputs. Its purpose is to aggregate all CP interrupts and report them to the AP through MSIs. The ICU writes into GIC registers (AP side) by way of the interconnect. These interrupts can be of several groups:
- SecuRe (SR);
- Non-SecuRe (NSR);
- System Error Interrupts (SEI);
- RAM Error Interrupts (REI);
- ...
Each ICU wired interrupt can be of any of these groups. The group is encoded in the MSI payload.
Quoted 4 lines
[...]
I'm now ready to queue patches 1 through to 11 (with patches 6 and 9 as of v7). Who is picking up the DT patches (12 to 14)?
I will do it.
Thanks,
Gregory
Quoted 7 lines
Thanks,
M.Signature · 1 line
Jazz is not dead, it just smell funny.
Signature · 3 lines
Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com