ARM: l2c: remove outer_inv_all() method
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- v1 Latest75 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/75 | ARM: l2c: remove outer_inv_all() methodarch/ arch/ arch/ | +0 | 0 replies | |
| 2/75 | ARM: l2c: remove unnecessary call to outer_flush_all()arch/ | +0 | 0 replies | |
| 3/75 | ARM: l2c: avoid calling outer_flush_all() unnecessarily (Spear)arch/ | +14 | 0 replies | |
| 4/75 | ARM: l2c: omap2: remove ES1.0 supportarch/ | +8 | 1 reply | |
| 5/75 | ARM: l2c: remove unnecessary UL-suffix to mask valuesarch/ arch/ arch/ +3 more | +6 | 2 replies | |
| 6/75 | ARM: outer cache: add documentation of outer cache functionsarch/ | +47 | 2 replies | |
| 7/75 | ARM: outer cache: add WARN_ON() to outer_disable()arch/ arch/ arch/ | +23 | 0 replies | |
| 8/75 | ARM: l2c: add helper for L2 cache controller DT IDsarch/ | +10 | 0 replies | |
| 9/75 | ARM: l2c: tidy up l2x0_of_data declarationsarch/ | +14 | 0 replies | |
| 10/75 | ARM: l2c: rename OF specific things, making l2x0_of_data available to allarch/ | +32 | 0 replies | |
| 11/75 | ARM: l2c: provide generic function for calling set_debug methodarch/ | +11 | 0 replies | |
| 12/75 | ARM: l2c: split out cache unlock codearch/ | +16 | 0 replies | |
| 13/75 | ARM: l2c: provide generic helper for way-based operationsarch/ | +9 | 0 replies | |
| 14/75 | ARM: l2c: rename cache_wait_way()arch/ | +3 | 0 replies | |
| 15/75 | ARM: l2c: add and use L2C revision constantsarch/ arch/ | +21 | 2 replies | |
| 16/75 | ARM: l2c: clean up OF initialisation a bitarch/ | +40 | 0 replies | |
| 17/75 | ARM: l2c: pass iomem address into data->save functionarch/ | +16 | 0 replies | |
| 18/75 | ARM: l2c: move l2c save function to __l2c_init()arch/ | +7 | 0 replies | |
| 19/75 | ARM: l2c: group implementation specific code togetherarch/ | +251 | 0 replies | |
| 20/75 | ARM: l2c: provide enable methodarch/ | +62 | 0 replies | |
| 21/75 | ARM: l2c: write auxctrl register before unlockingarch/ | +5 | 0 replies | |
| 22/75 | ARM: l2c: only write the auxiliary control register if requiredarch/ | +3 | 0 replies | |
| 23/75 | ARM: l2c: move aurora broadcast setup to enable functionarch/ | +15 | 0 replies | |
| 24/75 | ARM: l2c: implement fixups for L2 cache controller quirks/errataarch/ | +101 | 0 replies | |
| 25/75 | ARM: l2c: clean up L2 cache initialisation messagesarch/ | +4 | 0 replies | |
| 26/75 | ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OFarch/ | +77 | 0 replies | |
| 27/75 | ARM: l2c: clean up save/resume functionsarch/ | +52 | 0 replies | |
| 28/75 | ARM: l2c: simplify l2x0 unlocking codearch/ | +8 | 0 replies | |
| 29/75 | ARM: l2c: move pl310_set_debug() into l2c-310 codearch/ | +6 | 0 replies | |
| 30/75 | ARM: l2c: add L2C-210 specific handlersarch/ | +122 | 0 replies | |
| 31/75 | ARM: l2c: implement L2C-310 erratum 727915 as a method overridearch/ | +20 | 0 replies | |
| 32/75 | ARM: l2c: implement L2C-310 erratum 588369 as a method overridearch/ | +69 | 2 replies | |
| 33/75 | ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementationsarch/ | +36 | 0 replies | |
| 34/75 | ARM: l2c: add L2C-220 specific handlersarch/ | +157 | 0 replies | |
| 35/75 | ARM: l2c: convert Broadcom L2C-310 to new codearch/ | +11 | 0 replies | |
| 36/75 | ARM: l2c: remove obsolete l2x0 ops for non-OF initarch/ | +0 | 0 replies | |
| 37/75 | ARM: l2c: move type string into l2c_init_data structurearch/ | +13 | 0 replies | |
| 38/75 | ARM: l2c: add decode for L2C-220 cache waysarch/ | +1 | 0 replies | |
| 39/75 | ARM: l2c: move way size calculation data into l2c_init_dataarch/ | +20 | 0 replies | |
| 40/75 | ARM: l2c: move errata configuration options to arch/arm/mm/Kconfigarch/ arch/ | +51 | 0 replies | |
| 41/75 | ARM: l2c: provide generic hook to intercept writes to secure registersarch/ arch/ | +34 | 2 replies | |
| 42/75 | ARM: l2c: omap2: implement new write_sec methodarch/ | +26 | 1 reply | |
| 43/75 | ARM: l2c: omap2: remove explicit SMI calls to enable L2 cachearch/ | +0 | 1 reply | |
| 44/75 | ARM: l2c: highbank: implement new write_sec methodarch/ | +7 | 0 replies | |
| 45/75 | ARM: l2c: highbank: remove explicit SMI call in L2 cache initialisationarch/ | +1 | 0 replies | |
| 46/75 | ARM: l2c: ux500: implement dummy write_sec methodarch/ | +10 | 1 reply | |
| 47/75 | ARM: l2c: remove old .set_debug methodarch/ arch/ | +2 | 0 replies | |
| 48/75 | ARM: l2c: implement L2C-310 erratum 752271 in core L2C codearch/ | +17 | 0 replies | |
| 49/75 | ARM: l2c: fix register namingarch/ arch/ arch/ +11 more | +118 | 6 replies | |
| 50/75 | ARM: l2c: add automatic enable of early BRESParch/ | +22 | 0 replies | |
| 51/75 | ARM: l2c: remove platforms/SoCs setting early BRESParch/ arch/ arch/ +8 more | +19 | 1 reply | |
| 52/75 | ARM: l2c: tegra: remove associativity and way size from aux_ctrlarch/ | +1 | 0 replies | |
| 53/75 | ARM: l2c: ux500: remove associativity and way size from aux_ctrlarch/ | +2 | 1 reply | |
| 54/75 | ARM: l2c: ux500: don't try to change the L2 cache auxiliary control registerarch/ | +2 | 1 reply | |
| 55/75 | ARM: l2c: cns3xxx: remove cache size overridearch/ | +1 | 0 replies | |
| 56/75 | ARM: l2c: exynos: remove cache size overridearch/ | +1 | 0 replies | |
| 57/75 | ARM: l2c: nomadik: remove cache size overridearch/ | +1 | 1 reply | |
| 58/75 | ARM: l2c: omap2: remove cache size overridearch/ | +3 | 4 replies | |
| 59/75 | ARM: l2c: prima2: remove cache size overridearch/ arch/ arch/ | +3 | 3 replies | |
| 60/75 | ARM: l2c: shmobile: remove cache size overridearch/ arch/ arch/ +3 more | +6 | 0 replies | |
| 61/75 | ARM: l2c: spear13xx: remove cache size overridearch/ | +1 | 0 replies | |
| 62/75 | ARM: l2c: sti: remove cache size overridearch/ | +3 | 1 reply | |
| 63/75 | ARM: l2c: zynq: remove cache size overridearch/ | +1 | 7 replies | |
| 64/75 | ARM: l2c: realview: improve commentry about the L2 cache requirementsarch/ arch/ arch/ | +21 | 0 replies | |
| 65/75 | ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of thisarch/ | +0 | 0 replies | |
| 66/75 | ARM: l2c: print a warning with L2C-310 caches if the cache size is modifiedarch/ | +2 | 0 replies | |
| 67/75 | ARM: l2c: vexpress ca9x4: move L2 cache initialisation earlierarch/ | +18 | 0 replies | |
| 68/75 | ARM: l2c: add L2C-310 power control DT propertiesDocumentation/ arch/ arch/ +1 more | +16 | 0 replies | |
| 69/75 | ARM: l2c: check that DT files specify the required "cache-unified" propertyarch/ | +4 | 0 replies | |
| 70/75 | ARM: l2c: add warnings for stuff modifying aux_ctrl register valuesarch/ | +23 | 0 replies | |
| 71/75 | ARM: l2c: permit flush_all() on large flush_range() XXX Needs more thought XXXarch/ | +79 | 0 replies | |
| 72/75 | ARM: l2c: trial at enabling some Cortex-A9 optimisationsarch/ arch/ | +59 | 0 replies | |
| 73/75 | ARM: l2c: move L2 cache register saving to a more sensible locationarch/ | +9 | 7 replies | |
| 74/75 | ARM: l2c: always enable low power modesDocumentation/ arch/ | +12 | 5 replies | |
| 75/75 | ARM: l2c: imx: remove direct write to power control registerarch/ | +0 | 3 replies |
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Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 5 reviewers.