Xilinx Intc Fixes
Status from this message: Applied, thanks Peter.
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
Changes in v2 from the cover letter
Fixed S3ADSP UART interrupt - done first for bisectability (Now tested as working on s3asdsp design)
Patches in v2 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/5 | microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQhw/ | +1 | 0 replies | |
| 2/5 | intc/xilinx_intc: Don't clear level sens. IRQs without ACKhw/ | +1 | 0 replies | |
| 3/5 | intc/xilinx_intc: Handle level interrupt retriggeringhw/ | +15 | 0 replies | |
| 4/5 | intc/xilinx_intc: Inhibit write to ISR when HIEhw/ | +5 | 0 replies | |
| 5/5 | intc/xilinx_intc: Dont lower IRQ when HIE clearedhw/ | +0 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v2 yet.
Cover letter [Qemu-devel] [PATCH v2 0/5] Xilinx Intc Fixes
From: Peter Crosthwaite <[email protected]>
Various fixups to the Xilinx Interrupt controller following a review against TRM and RTL descriptions.
Tested as working for microblaze and microblazeel Linux.
change from v1:
Fixed S3ADSP UART interrupt - done first for bisectability (Now tested as working on s3asdsp design)
Peter Crosthwaite (5):
microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ intc/xilinx_intc: Don't clear level sens. IRQs without ACK intc/xilinx_intc: Handle level interrupt retriggering intc/xilinx_intc: Inhibit write to ISR when HIE intc/xilinx_intc: Dont lower IRQ when HIE cleared
hw/intc/xilinx_intc.c | 28 ++++++++++++++++++---------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- 2 files changed, 19 insertions(+), 11 deletions(-)
Signature · 1 line
1.8.3.rc1.44.gb387c77.dirty