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RFC Per Master Addressing (PMA)

Peter Crosthwaite qemu-devel 1 version In review

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  1. v1 RFC Latest11 patches 6 repliesIn review

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/11microblaze: ml605: Get rid of useless ddr_base variablehw/microblaze/petalogix_ml605_mmu.c+2 -30 replies
2/11dma: axidma: Variablise repeated s->streams[i] sub-exprhw/dma/xilinx_axidma.c+5 -40 replies
3/11exec: Parent root MRs to the machineexec.c+4 -00 replies
4/11exec: dummy_section: Pass address space through.exec.c+8 -60 replies
5/11memory: Parent Memory Regions to their registered ownersmemory.c+19 -00 replies
6/11memory: address_space_init: do nothing if no root region givenmemory.c+4 -00 replies
7/11memory.c: Add address_space_init_shareable()include/exec/memory.h memory.c+26 -02 replies
8/11qom/cpu: Add Memory Region Propertyinclude/qom/cpu.h qom/cpu.c+31 -00 replies
9/11exec: use per-cpu address-spaces for cpuismsexec.c hw/core/loader.c+4 -32 replies
10/11microblaze: ml605: Convert to PMAhw/microblaze/petalogix_ml605_mmu.c+26 -90 replies
11/11dma: axidma: Convert to PMAhw/dma/xilinx_axidma.c hw/microblaze/petalogix_ml605_mmu.c+37 -50 replies

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Cover letter [Qemu-devel] [RFC PATCH v1 00/11] Per Master Addressing (PMA)

Hi All,

This series implements Per-bus-Master Address spaces (PMA). It builds on the merged components of Edgar's original series:

https://lists.gnu.org/archive/html/qemu-devel/2014-02/msg01346.html

And my pending MemoryRegion QOMification:

https://lists.nongnu.org/archive/html/qemu-devel/2014-06/msg00029.html

The approach is based on PMA as discussed KVM call 2014-05-13. MOM:

http://lists.gnu.org/archive/html/qemu-devel/2014-05/msg02430.html

"
PM: Address space is flattended memory regions, needed for actual memory access when constructing machines, we deal with memory regions, not address spaces

AF+PM: Each CPU should have its own address space

...

Do busmasters get their own address space, too?
PM: Yes
"

Patches 3-9 patch memory, exec and CPU to enable this capability generally. The basic idea is MemoryRegions are QOM/linkable, and masters create their own AddressSpace as needed from their given MRs.

The PetaLogix ml605 board is converted to use the new framework as the lead example P10/11. It is tested as working. For a diagram of the real hardware setup WRT to DMA and bus master visibility:

http://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v6_03_a/pg021_axi_dma.pdf

page 49.

This series is work-in-progress and has numerous FIXMEs in it. Looking for conceptual level commentary.

2 trivials at the front of the series. Easily skipped by reviewers.

Regards,
Peter

Peter Crosthwaite (11):
microblaze: ml605: Get rid of useless ddr_base variable
dma: axidma: Variablise repeated s->streams[i] sub-expr
exec: Parent root MRs to the machine
exec: dummy_section: Pass address space through.
memory: Parent Memory Regions to their registered owners
memory: address_space_init: do nothing if no root region given memory.c: Add address_space_init_shareable() qom/cpu: Add Memory Region Property
exec: use per-cpu address-spaces for cpuisms
microblaze: ml605: Convert to PMA
dma: axidma: Convert to PMA

 exec.c                              | 23 +++++++++++-------
 hw/core/loader.c                    |  2 +-
 hw/dma/xilinx_axidma.c              | 47 ++++++++++++++++++++++++++++++-------
 hw/microblaze/petalogix_ml605_mmu.c | 42 ++++++++++++++++++++++++---------
 include/exec/memory.h               |  2 ++
 include/qom/cpu.h                   |  1 +
 memory.c                            | 47 +++++++++++++++++++++++++++++++++++++
 qom/cpu.c                           | 30 +++++++++++++++++++++++
 8 files changed, 165 insertions(+), 29 deletions(-)
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