x86, mpx: Instruction decoder fixes and hardening
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v4 Latest2 patches 6 repliesIn review
- v32 patches 0 repliesSuperseded
- v23 patches 7 repliesSuperseded
Changes in v4 from the cover letter
- Replaced MAX_INSN_SIZE with 15 in the decoder change. (Masami) I'll send the patch for 3.20 to fix MAX_INSN_SIZE separately.
Patches in v4 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/2 | x86, mpx: Short-circuit the instruction decoder for unexpected opcodesarch/ | +16 | 2 replies | |
| 2/2 | x86: Enforce maximum instruction size in the instruction decoderarch/ | +7 | 4 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v4 yet.
Cover letter [PATCH 3.19 v4 0/2] x86, mpx: Instruction decoder fixes and hardening
Hi all-
Ingo and Thomas, I think this is in decent shape for x86/urgent now if you think it's appropriate to apply at this point in the cycle.
Changes from v3:
- Replaced MAX_INSN_SIZE with 15 in the decoder change. (Masami) I'll send the patch for 3.20 to fix MAX_INSN_SIZE separately.
Changes from v2:
- Dropped patch 1 (fixed in tip separately)
- Fixed comment typoes in patch 2 (noticed by Dave)
Changes from v1:
- Dropped the TIF_IA32 change -- let's defer that until at least 3.20.
- Fixed the MPX decode short-circuit. v1 was buggy.
- Patch 3 is new. It fixes a minor regression from the MPX work.
Andy Lutomirski (2):
x86, mpx: Short-circuit the instruction decoder for unexpected opcodes
x86: Enforce maximum instruction size in the instruction decoder
arch/x86/lib/insn.c | 7 +++++++ arch/x86/mm/mpx.c | 25 ++++++++++++++++--------- 2 files changed, 23 insertions(+), 9 deletions(-)
Signature · 1 line
2.1.0