Next Generation Xilinx Zynq SoC
Status from this message: Applied to target-arm.next, thanks.
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v9 Latest14 patches 1 replyApplied
- v814 patches 3 repliesSuperseded
- v715 patches 7 repliesSuperseded
Earlier versions · 6
| Version | Posted | Patches | Replies | Status |
|---|---|---|---|---|
| v6 | 11 of 14 patches | 24 replies | Superseded | |
| v5 | 12 of 14 patches | 1 reply | Superseded | |
| v4 | 14 of 16 patches | 39 replies | Superseded | |
| v3 | 12 of 15 patches | 8 replies | Superseded | |
| v2 | 12 of 15 patches | 5 replies | Superseded | |
| v1 | 15 patches | 25 replies | Superseded |
Changes in v9 from the cover letter
Correct GIC nr of SPIs (=160)
Patches in v9 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/14 | target-arm: cpu64: generalise name of A57 regstarget-arm/ | +5 | 0 replies | |
| 2/14 | target-arm: cpu64: Add support for Cortex-A53target-arm/ | +51 | 0 replies | |
| 3/14 | arm: Introduce Xilinx ZynqMP SoCdefault-configs/ hw/ hw/ +1 more | +116 | 0 replies | |
| 4/14 | arm: xlnx-zynqmp: Add GIChw/ include/ | +73 | 0 replies | |
| 5/14 | arm: xlnx-zynqmp: Connect CPU Timers to GIChw/ | +17 | 0 replies | |
| 6/14 | net: cadence_gem: Clean up variable nameshw/ | +35 | 0 replies | |
| 7/14 | net: cadence_gem: Split state struct and type into headerhw/ include/ | +74 | 0 replies | |
| 8/14 | arm: xlnx-zynqmp: Add GEM supporthw/ include/ | +38 | 0 replies | |
| 9/14 | char: cadence_uart: Clean up variable nameshw/ | +54 | 0 replies | |
| 10/14 | char: cadence_uart: Split state struct and type into headerhw/ include/ | +54 | 0 replies | |
| 11/14 | arm: xlnx-zynqmp: Add UART supporthw/ include/ | +27 | 0 replies | |
| 12/14 | arm: Add xlnx-ep108 machinehw/ hw/ | +54 | 0 replies | |
| 13/14 | arm: xlnx-ep108: Add external RAMhw/ | +20 | 0 replies | |
| 14/14 | arm: xlnx-ep108: Add bootloadinghw/ | +9 | 0 replies |
Reviews trailers per patch
13 of 14 patches have a Reviewed-by or Acked-by.
| Patch | Edgar E. Iglesias | Peter Maydell | Alistair Francis | Alex Bennée |
|---|---|---|---|---|
| 1/14 | R-b | R-b | ||
| 2/14 | A-b | R-b | ||
| 3/14 | R-b | T-b R-b | ||
| 4/14 | ||||
| 5/14 | R-b | T-b | ||
| 6/14 | R-b | R-b | R-b T-b | R-b |
| 7/14 | R-b | R-b | R-b T-b | |
| 8/14 | R-b | T-b | ||
| 9/14 | R-b | R-b | R-b T-b | |
| 10/14 | R-b | R-b | R-b T-b | |
| 11/14 | R-b | R-b T-b | ||
| 12/14 | R-b | R-b | R-b T-b | |
| 13/14 | R-b T-b | |||
| 14/14 | R-b T-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 4 reviewers.
Cover letter [Qemu-devel] [PATCH target-arm v9 00/14] Next Generation Xilinx Zynq SoC
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and board.
Series start with addition of ARM cortex A53 support (P1 and P2). The Soc skeleton is then added with GIC, EMACs and UARTs added. The pre-existing models for GEM and UART are not SoC friendly (no visible state struct), so those are refactored for SoC.
Create a model of the EP108 board. Currently this doesn't have any EP108 specific features but is a usable board exposing the user visible features of the raw SoC.
See individual patches for detailed change logs.
changed since v8 (Edgar review):
Correct GIC nr of SPIs (=160)
changed since v7 (PMM review):
made GIC region sz defs board specific.
changed since v6 (Edgar review):
Added GIC region size macro
Added GIC alises
changed since v4:
Addressed PMM and Alistair Reviews
changed since v3:
Included CPU thread kick fix
Addressed Alistair review
changed since v2:
Fix CPU child prop adder
Add DTS compat string
changed since v1:
Addressed Alistair review (individual changes on resp. patches) Changed board name to EP108
Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review)
Regards,
Peter
Peter Crosthwaite (14):
target-arm: cpu64: generalise name of A57 regs
target-arm: cpu64: Add support for Cortex-A53
arm: Introduce Xilinx ZynqMP SoC
arm: xlnx-zynqmp: Add GIC
arm: xlnx-zynqmp: Connect CPU Timers to GIC
net: cadence_gem: Clean up variable names
net: cadence_gem: Split state struct and type into header
arm: xlnx-zynqmp: Add GEM support
char: cadence_uart: Clean up variable names
char: cadence_uart: Split state struct and type into header
arm: xlnx-zynqmp: Add UART support
arm: Add xlnx-ep108 machine
arm: xlnx-ep108: Add external RAM
arm: xlnx-ep108: Add bootloading
default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-ep108.c | 82 ++++++++++++++ hw/arm/xlnx-zynqmp.c | 211 ++++++++++++++++++++++++++++++++++++ hw/char/cadence_uart.c | 115 ++++++++------------ hw/net/cadence_gem.c | 95 +++++----------- include/hw/arm/xlnx-zynqmp.h | 58 ++++++++++ include/hw/char/cadence_uart.h | 53 +++++++++ include/hw/net/cadence_gem.h | 73 +++++++++++++ target-arm/cpu64.c | 61 ++++++++++- 10 files changed, 609 insertions(+), 142 deletions(-) create mode 100644 hw/arm/xlnx-ep108.c create mode 100644 hw/arm/xlnx-zynqmp.c create mode 100644 include/hw/arm/xlnx-zynqmp.h create mode 100644 include/hw/char/cadence_uart.h create mode 100644 include/hw/net/cadence_gem.h
Signature · 1 line
2.4.0.3.ge0ccc3b.dirty