ARM Cortex R5 Support
Status from this message: Thanks, applied to target-arm.next. (This is by a few days
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v3 Latest7 patches 8 repliesApplied
- v213 patches 8 repliesSuperseded
- v19 patches 25 repliesSuperseded
Changes in v3 from the cover letter
Rebased (early patches merged)
Added boot CPU selection.
Addressed PMM review (see indiv. patches)
Patches in v3 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/7 | target-arm/helper.c: define MPUIR registertarget-arm/ target-arm/ target-arm/ | +30 | 0 replies | |
| 2/7 | target-arm: Add registers for PMSAv7target-arm/ target-arm/ target-arm/ +1 more | +133 | 0 replies | |
| 3/7 | target-arm: Implement PMSAv7 MPUtarget-arm/ target-arm/ | +174 | 0 replies | |
| 4/7 | target-arm: Add support for Cortex-R5target-arm/ | +38 | 1 reply | |
| 5/7 | arm: xlnx-zynqmp: Preface CPU variables with "apu"hw/ hw/ include/ | +17 | 1 reply | |
| 6/7 | arm: xlnx-zynqmp: Add boot-cpu propertyhw/ hw/ include/ | +22 | 0 replies | |
| 7/7 | arm: xlnx-zynqmp: Add 2xCortexR5 CPUshw/ include/ | +36 | 5 replies |
Reviews trailers per patch
4 of 7 patches have a Reviewed-by or Acked-by.
| Patch | Peter Maydell | Edgar E. Iglesias |
|---|---|---|
| 1/7 | ||
| 2/7 | R-b | |
| 3/7 | R-b | |
| 4/7 | R-b | R-b |
| 5/7 | R-b | |
| 6/7 | ||
| 7/7 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [Qemu-devel] [PATCH target-arm v3 0/7] ARM Cortex R5 Support
Hi Peter and all,
This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU is implemented. Two R5s are added to the Xilinx ZynqMP SoC.
Changed since v2:
Rebased (early patches merged)
Added boot CPU selection.
Addressed PMM review (see indiv. patches)
Changed since v1:
Addressed PMM and Alistair reviews (see indiv. patches) Adding prepatory refactorings to target-arm (new patches)
- TLBTR VMSA conditional (1)
- V7MP CP regs VMSA conditional (2)
- Refactor get_phys_addr FSR return path (4)
- Add MPUIR.U config (5)
- Improved cpu configurability around MPUs (6-7)
Regards,
Peter
Peter Crosthwaite (7):
target-arm/helper.c: define MPUIR register
target-arm: Add registers for PMSAv7
target-arm: Implement PMSAv7 MPU
target-arm: Add support for Cortex-R5
arm: xlnx-zynqmp: Preface CPU variables with "apu"
arm: xlnx-zynqmp: Add boot-cpu property
arm: xlnx-zynqmp: Add 2xCortexR5 CPUs
hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 79 +++++++++++-- include/hw/arm/xlnx-zynqmp.h | 9 +- target-arm/cpu-qom.h | 2 + target-arm/cpu.c | 62 ++++++++++ target-arm/cpu.h | 11 ++ target-arm/helper.c | 274 +++++++++++++++++++++++++++++++++++++++++-- target-arm/machine.c | 34 ++++++ 8 files changed, 449 insertions(+), 24 deletions(-)
Signature · 1 line
2.4.3.3.g905f831