pci: xgene: Add multiple memory ranges support
Status from this message: Applied to pci/host-xgene for v4.3, with changelogs as follows, thanks!
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- v3 Latest2 patches 2 repliesApplied
- v22 patches 3 repliesSuperseded
Changes in v3 from the cover letter
1. Explicitly mention in change log that: Each PCIe node in dts will have 1 32-bit non-prefetchable memory window and 1 64-bit prefetchable memory window.
Patches in v3 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/2 | arm64: dts: Add 1 more window with large size for X-Gene PCIe nodesarch/ | +14 | 0 replies | |
| 2/2 | pci: xgene: Fix driver to handle multiple memory rangesdrivers/ | +10 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v3 yet.
Cover letter [PATCH v3 0/2] pci: xgene: Add multiple memory ranges support
This patch set adds 1 large (up to 64GB) memory window for each PCIe controller nodes in X-Gene device tree and fix PCIe controller driver to handle multiple memory ranges correctly. These changes are required to support PCIe devices that have huge BAR.
v3 changes:
1. Explicitly mention in change log that: Each PCIe node in dts will have 1 32-bit non-prefetchable memory window and 1 64-bit prefetchable memory window.
v2 changes:
1. Separate device-tree changes and driver changes into different patches
2. Explicitly define new large window as 64-bit prefetchable in dts.
3. Use IORESOURCE_PREFETCH flag to determine which PCIe controller register to be used to configure the memory ranges.
arch/arm64/boot/dts/apm/apm-storm.dtsi | 23 ++++++++++++++--------- drivers/pci/host/pci-xgene.c | 12 ++++++++++-- 2 files changed, 24 insertions(+), 11 deletions(-)
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1.9.1