RFC x86/mm: PCID and INVPCID
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b4 am [email protected]Versions newest first
- v1 RFC Latest13 patches 23 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/13 | x86/paravirt: Turn KASAN off for parvirt.oarch/ | +1 | 7 replies | |
| 2/13 | x86/mm: Add INVPCID helpersarch/ | +41 | 0 replies | |
| 3/13 | x86/mm: Add a noinvpcid option to turn off INVPCIDDocumentation/ arch/ | +18 | 0 replies | |
| 4/13 | x86/mm: If INVPCID is available, use it to flush global mappingsarch/ | +9 | 0 replies | |
| 5/13 | x86/mm: Add barriers and document switch_mm-vs-flush synchronizationarch/ arch/ | +58 | 4 replies | |
| 6/13 | x86/mm: Disable PCID on 32-bit kernelsarch/ arch/ | +9 | 0 replies | |
| 7/13 | x86/mm: Add nopcid to turn off PCIDDocumentation/ arch/ | +20 | 0 replies | |
| 8/13 | x86/mm: Teach CR3 readers about PCIDarch/ arch/ arch/ | +14 | 0 replies | |
| 9/13 | x86/mm: Disable interrupts when flushing the TLB using CR3arch/ | +10 | 10 replies | |
| 10/13 | x86/mm: Factor out remote TLB flushingarch/ | +11 | 0 replies | |
| 11/13 | x86/mm: Build arch/x86/mm/tlb.c even on !SMParch/ arch/ | +5 | 1 reply | |
| 12/13 | x86/mm: Uninline switch_mmarch/ arch/ | +99 | 0 replies | |
| 13/13 | x86/mm: Try to preserve old TLB entries using PCIDarch/ arch/ arch/ +3 more | +213 | 2 replies |
Reviews trailers per patch
None of the 13 patches has a Reviewed-by or Acked-by.
| Patch | Andy Lutomirski |
|---|---|
| 1/13 | T-b |
| 2/13 | |
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Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [RFC 00/13] x86/mm: PCID and INVPCID
Here's my PCID and INVPCID work-in-progress. It seems to work well enough to play with it. (That is, I'm not aware of anything wrong with it, although it may eat your data.)
PCID and INVPCID use are orthogonal here. INVPCID is a straightforward speedup for global TLB flushes. Other than that, I don't use INVPCID at all, since it seems slower than just manipulating CR3 carefully, at least on my Skylake laptop.
Please play around and suggest (and run?) good benchmarks. It seems to save around 100ns on cross-process context switches for me. Unfortunately, we suck at context switches in general, so this is, at best, a little over a 10% speedup. Most of the time is spent in the scheduler, not in arch code.
Andy Lutomirski (13):
x86/paravirt: Turn KASAN off for parvirt.o
x86/mm: Add INVPCID helpers
x86/mm: Add a noinvpcid option to turn off INVPCID x86/mm: If INVPCID is available, use it to flush global mappings x86/mm: Add barriers and document switch_mm-vs-flush synchronization x86/mm: Disable PCID on 32-bit kernels
x86/mm: Add nopcid to turn off PCID
x86/mm: Teach CR3 readers about PCID
x86/mm: Disable interrupts when flushing the TLB using CR3 x86/mm: Factor out remote TLB flushing
x86/mm: Build arch/x86/mm/tlb.c even on !SMP
x86/mm: Uninline switch_mm
x86/mm: Try to preserve old TLB entries using PCID
Documentation/kernel-parameters.txt | 4 + arch/x86/include/asm/disabled-features.h | 4 +- arch/x86/include/asm/mmu.h | 7 +- arch/x86/include/asm/mmu_context.h | 62 +----- arch/x86/include/asm/tlbflush.h | 86 ++++++++ arch/x86/kernel/Makefile | 1 + arch/x86/kernel/cpu/bugs.c | 6 + arch/x86/kernel/cpu/common.c | 38 ++++ arch/x86/kernel/head64.c | 3 +- arch/x86/kernel/ldt.c | 2 + arch/x86/kernel/process_64.c | 2 + arch/x86/mm/Makefile | 3 +- arch/x86/mm/fault.c | 8 +- arch/x86/mm/tlb.c | 324 +++++++++++++++++++++++++++++-- 14 files changed, 467 insertions(+), 83 deletions(-)
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