Lockless Access Tracking for Intel CPUs without EPT A bits
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- v3 Latest8 patches 19 repliesIn review
- v25 patches 13 repliesSuperseded
- v14 patches 4 repliesSuperseded
Changes in v3 from the cover letter
* Added two patches to refactor mmu_spte_update/clear and add a no_track version of mmu_spte_update.
* Ensured that fast_page_fault handles non-write faults to large pages that are being access tracked.
* Several minor changes based on code review feedback from v2.
Patches in v3 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/8 | kvm: x86: mmu: Use symbolic constants for EPT Violation Exit Qualificationsarch/ arch/ | +30 | 2 replies | |
| 2/8 | kvm: x86: mmu: Rename spte_is_locklessly_modifiable()arch/ | +5 | 1 reply | |
| 3/8 | kvm: x86: mmu: Fast Page Fault path retriesarch/ | +73 | 4 replies | |
| 4/8 | kvm: x86: mmu: Refactor accessed/dirty checks in mmu_spte_update/cleararch/ | +32 | 0 replies | |
| 5/8 | kvm: x86: mmu: Introduce a no-tracking version of mmu_spte_updatearch/ | +28 | 0 replies | |
| 6/8 | kvm: x86: mmu: Do not use bit 63 for tracking special SPTEsarch/ arch/ arch/ | +17 | 0 replies | |
| 7/8 | kvm: x86: mmu: Lockless access tracking for Intel CPUs without EPT A bits.arch/ arch/ arch/ +2 more | +237 | 12 replies | |
| 8/8 | kvm: x86: mmu: Update documentation for fast page fault mechanismDocumentation/ | +27 | 0 replies |
Reviews trailers per patch
2 of 8 patches have a Reviewed-by or Acked-by.
| Patch | Paolo Bonzini | Xiao Guangrong |
|---|---|---|
| 1/8 | R-b | |
| 2/8 | R-b | R-b |
| 3/8 | ||
| 4/8 | ||
| 5/8 | ||
| 6/8 | ||
| 7/8 | ||
| 8/8 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v3 0/8] Lockless Access Tracking for Intel CPUs without EPT A bits
Changes from v2:
* Added two patches to refactor mmu_spte_update/clear and add a no_track version of mmu_spte_update.
* Ensured that fast_page_fault handles non-write faults to large pages that are being access tracked.
* Several minor changes based on code review feedback from v2.
Changes from v1:
* Patch 1 correctly maps to the current codebase by setting the Present bit in the page fault error code if any of the Readable, Writeable or Executable bits are set in the Exit Qualification.
* Added Patch 5 to update Documentation/virtual/kvm/locking.txt
This patch series implements a lockless access tracking mechanism for KVM when running on Intel CPUs that do not have EPT A/D bits.
Currently, KVM tracks accesses on these machines by just clearing the PTEs and then remapping them when they are accessed again. However, the remapping requires acquiring the MMU lock in order to lookup the information needed to construct the PTE. On high core count VMs, this can result in significant MMU lock contention when running some memory-intesive workloads.
This new mechanism just marks the PTEs as not-present, but keeps all the information within the PTE instead of clearing it. When the page is accessed again, the PTE can thus be restored without needing to acquire the MMU lock.
Junaid Shahid (8):
kvm: x86: mmu: Use symbolic constants for EPT Violation Exit
Qualifications
kvm: x86: mmu: Rename spte_is_locklessly_modifiable()
kvm: x86: mmu: Fast Page Fault path retries
kvm: x86: mmu: Refactor accessed/dirty checks in mmu_spte_update/clear
kvm: x86: mmu: Introduce a no-tracking version of mmu_spte_update
kvm: x86: mmu: Do not use bit 63 for tracking special SPTEs
kvm: x86: mmu: Lockless access tracking for Intel CPUs without EPT A
bits.
kvm: x86: mmu: Update documentation for fast page fault mechanism
Documentation/virtual/kvm/locking.txt | 31 ++- arch/x86/include/asm/kvm_host.h | 10 +- arch/x86/include/asm/vmx.h | 28 +- arch/x86/kvm/mmu.c | 464 +++++++++++++++++++++++----------- arch/x86/kvm/vmx.c | 54 ++-- arch/x86/kvm/x86.c | 2 +- 6 files changed, 419 insertions(+), 170 deletions(-)
Signature · 1 line
2.8.0.rc3.226.g39d4020