drm/i915/dp: link rate and lane count refactoring
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- v3 Latest14 patches 17 repliesIn review
- v213 patches 5 repliesSuperseded
- v113 patches 16 repliesSuperseded
Patches in v3 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/14 | drm/i915/dp: use known correct array size in rate_to_indexdrivers/ | +6 | 1 reply | |
| 2/14 | drm/i915/dp: return errors from rate_to_index()drivers/ | +9 | 3 replies | |
| 3/14 | drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reusedrivers/ | +15 | 1 reply | |
| 4/14 | drm/i915/dp: cache source rates at initdrivers/ drivers/ | +24 | 1 reply | |
| 5/14 | drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4drivers/ drivers/ drivers/ | +61 | 2 replies | |
| 6/14 | drm/i915/dp: use the sink rates array for max sink ratesdrivers/ drivers/ | +8 | 0 replies | |
| 7/14 | drm/i915/dp: cache common rates with sink ratesdrivers/ drivers/ | +45 | 1 reply | |
| 8/14 | drm/i915/dp: do not limit rate seek when not neededdrivers/ | +12 | 3 replies | |
| 9/14 | drm/i915/dp: don't call the link parameters sink parametersdrivers/ drivers/ | +16 | 1 reply | |
| 10/14 | drm/i915/dp: add functions for max common link rate and lane countdrivers/ | +17 | 1 reply | |
| 11/14 | drm/i915/mst: use max link not sink lane countdrivers/ drivers/ drivers/ | +4 | 1 reply | |
| 12/14 | drm/i915/dp: localize link rate index variable moredrivers/ | +7 | 3 replies | |
| 13/14 | drm/i915/dp: use readb and writeb calls for single byte DPCD accessdrivers/ | +17 | 1 reply | |
| 14/14 | drm/i915/dp: read sink count to a temporary variable firstdrivers/ | +4 | 0 replies |
Reviews trailers per patch
11 of 14 patches have a Reviewed-by or Acked-by.
| Patch | Manasi Navare |
|---|---|
| 1/14 | R-b |
| 2/14 | R-b |
| 3/14 | R-b |
| 4/14 | R-b |
| 5/14 | R-b |
| 6/14 | |
| 7/14 | R-b |
| 8/14 | R-b |
| 9/14 | R-b |
| 10/14 | R-b |
| 11/14 | |
| 12/14 | R-b |
| 13/14 | R-b |
| 14/14 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v3 00/14] drm/i915/dp: link rate and lane count refactoring
v3 of [1], rebased and review addressed.
This might still conflict with some of Manasi's pending work, but I think for the most parts we could start pushing these. The scales are tipping, it'll be easier to rebase Manasi's stuff than this. Indeed some of it may be easier to understand after the changes here.
BR,
Jani.
[1] http://mid.mail-archive.com/[email protected]
Jani Nikula (14):
drm/i915/dp: use known correct array size in rate_to_index drm/i915/dp: return errors from rate_to_index() drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse drm/i915/dp: cache source rates at init
drm/i915/dp: generate and cache sink rate array for all DP, not just
eDP 1.4
drm/i915/dp: use the sink rates array for max sink rates drm/i915/dp: cache common rates with sink rates drm/i915/dp: do not limit rate seek when not needed drm/i915/dp: don't call the link parameters sink parameters drm/i915/dp: add functions for max common link rate and lane count drm/i915/mst: use max link not sink lane count drm/i915/dp: localize link rate index variable more drm/i915/dp: use readb and writeb calls for single byte DPCD access drm/i915/dp: read sink count to a temporary variable first
drivers/gpu/drm/i915/intel_dp.c | 291 ++++++++++++++------------ drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +- drivers/gpu/drm/i915/intel_dp_mst.c | 4 +- drivers/gpu/drm/i915/intel_drv.h | 20 +- 4 files changed, 179 insertions(+), 139 deletions(-)
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