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drm/i915/dp: rest of refactoring, link rate fallback

Jani Nikula intel-gfx 1 version In review

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  1. v4 Latest11 patches 8 repliesIn review

Patches in v4 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/11drm/i915/dp: use the sink rates array for max sink ratesdrivers/gpu/drm/i915/intel_dp.c drivers/gpu/drm/i915/intel_drv.h+8 -221 reply
2/11drm/i915/dp: cache common rates with sink ratesdrivers/gpu/drm/i915/intel_dp.c drivers/gpu/drm/i915/intel_drv.h+45 -330 replies
3/11drm/i915/dp: do not limit rate seek when not neededdrivers/gpu/drm/i915/intel_dp.c+12 -190 replies
4/11drm/i915/dp: don't call the link parameters sink parametersdrivers/gpu/drm/i915/intel_dp.c drivers/gpu/drm/i915/intel_drv.h+16 -170 replies
5/11drm/i915/dp: add functions for max common link rate and lane countdrivers/gpu/drm/i915/intel_dp.c+17 -120 replies
6/11drm/i915/mst: use max link not sink lane countdrivers/gpu/drm/i915/intel_dp.c drivers/gpu/drm/i915/intel_dp_mst.c drivers/gpu/drm/i915/intel_drv.h+4 -30 replies
7/11drm/i915/dp: localize link rate index variable moredrivers/gpu/drm/i915/intel_dp.c+7 -60 replies
8/11drm/i915/dp: use readb and writeb calls for single byte DPCD accessdrivers/gpu/drm/i915/intel_dp.c+17 -200 replies
9/11drm/i915/dp: read sink count to a temporary variable firstdrivers/gpu/drm/i915/intel_dp.c+4 -33 replies
10/11drm/i915/dp: Validate cached link rate and lane count before retrainingdrivers/gpu/drm/i915/intel_dp.c+27 -37 replies
11/11drm/i915: Implement Link Rate fallback on Link training failuredrivers/gpu/drm/i915/intel_dp.c drivers/gpu/drm/i915/intel_dp_link_training.c drivers/gpu/drm/i915/intel_drv.h+50 -22 replies

Reviews trailers per patch

All 11 patches have a Reviewed-by or Acked-by.

PatchManasi NavareTony ChengHarry WentlandJani NikulaVille Syrjälä
1/11R-b
2/11R-b
3/11R-b
4/11R-b
5/11R-b
6/11R-b
7/11R-b
8/11R-b
9/11R-b
10/11R-b
11/11A-b A-b R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 5 reviewers.

Read the v4 thread

Cover letter [PATCH v4 00/11] drm/i915/dp: rest of refactoring, link rate fallback

v4 of [1], after patches 1-5 have been merged, and with Manasi's patches [2] and
[3] rebased on top.

BR,
Jani.

[1] http://mid.mail-archive.com/[email protected]
[2] http://patchwork.freedesktop.org/patch/msgid/[email protected]
[3] http://patchwork.freedesktop.org/patch/msgid/[email protected]

Jani Nikula (9):
drm/i915/dp: use the sink rates array for max sink rates drm/i915/dp: cache common rates with sink rates drm/i915/dp: do not limit rate seek when not needed drm/i915/dp: don't call the link parameters sink parameters drm/i915/dp: add functions for max common link rate and lane count drm/i915/mst: use max link not sink lane count drm/i915/dp: localize link rate index variable more drm/i915/dp: use readb and writeb calls for single byte DPCD access drm/i915/dp: read sink count to a temporary variable first

Manasi Navare (2):
drm/i915/dp: Validate cached link rate and lane count before
retraining
drm/i915: Implement Link Rate fallback on Link training failure

 drivers/gpu/drm/i915/intel_dp.c               | 236 +++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dp_link_training.c |  22 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c           |   4 +-
 drivers/gpu/drm/i915/intel_drv.h              |  15 +-
 4 files changed, 172 insertions(+), 105 deletions(-)
Signature · 6 lines
2.1.4

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